SI3215MPPQX-EVB Silicon Laboratories Inc, SI3215MPPQX-EVB Datasheet - Page 42

• Manufacturer Part Number: SI3215MPPQX-EVB
• Description: BOARD EVAL W/DISCRETE INTERFACE
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3215MPPQX-EVB

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: Si3215
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si3215
2.7. Two-Wire Impedance Matching
The ProSLIC provides on-chip, programmable two-wire
impedance settings to meet a wide variety of worldwide
two-wire return loss requirements. The two-wire
impedance is programmed by loading one of the eight
available impedance values into the TISS[2:0] bits of the
Two-Wire Impedance Synthesis Control register (direct
Register 10). If direct Register 10 is not user-defined,
the default setting of 600 Ω will be loaded into the TISS
register.
Real and complex two-wire impedances are realized by
internal feedback of a programmable amplifier (RAC) a
switched
transconductance amplifier (G
creates the real portion and XAC creates the imaginary
portion of G
models the desired impedance value to the subscriber
loop. The differential ac current is fed to the subscriber
loop via the ITIPP and IRINGP pins through an off-chip
current buffer (I
transistor Q1 and Q2 (see Figure on page 20). G
referenced to an off-chip resistor (R
42
the receive path.
An additional analog loopback (ALM1) takes the
digital stream at the output of the A/D converter and
feeds it back to the D/A converter. (See Figure 22.)
The signal path starts with the analog signal at the
input of the transmit path and ends with an analog
signal at the output of the receive path. This
loopback option allows the testing of the analog
signal processing circuitry of the Si3215 completely
independently of any activity in the DSP.
The full digital loopback tests almost all the circuitry
of both the transmit and receive paths. The analog
signal at the output of the receive path is fed back to
the input of the transmit path by way of the hybrid
filter path. (See Figure 22.) The signal path starts
with 8-bit PCM data input to the receive path and
ends with 8-bit PCM data at the output of the
transmit path. The user can bypass the companding
process and interface directly to the 16-bit data.
An additional digital loopback (DLM) takes the digital
stream at the input of the D/A converter in the
receive path and feeds it back to the transmit A/D
digital filter. The signal path starts with 8-bit PCM
data input to the receive path and ends with 8-bit
PCM data at the output of the transmit path. This
loopback option allows the testing of the digital
signal processing circuitry of the Si3215 completely
independently of any analog signal processing
activity. The user can bypass the companding
process and interface directly to the 16-bit data.
capacitor
m
’s input. G
BUF
), which is implemented using
m
network
then creates a current that
m
). (See Figure 22.) RAC
15
(XAC)
).
and
m
Rev. 0.92
is
a
The ProSLIC also provides a means of compensating
for degraded subscriber loop conditions involving
excessive line capacitance (leakage). The CLC[1:0] bits
of direct Register 10 increase the ac signal magnitude
to compensate for the additional loss at the high end of
the audio frequency range. The default setting of
CLC[2:0] assumes no line capacitance.
The Si3215 supports the option to remove the internal
reference resistor used to synthesize ac impedances for
600 + 1 µF and 900 + 2.16 µF settings so that an
external resistor reference may be used. This option is
enabled by setting ZSEXT = 1 (direct Register 108,
bit 4). When 600 + 1 µF or 900 + 2.16 µF impedances
are selected, an internal reference resistor is removed
from the impedance synthesis circuit to accommodate
an external resistor, R
application circuit as shown in Figure 23.
2.8. Clock Generation
The ProSLIC will generate the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 768 kHz,
1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz, or
8.192 MHz. The ratio of the PCLK rate to the FSYNC
rate is determined via a counter clocked by PCLK. The
three-bit ratio information is automatically transferred
into an internal register, PLL_MULT, following a reset of
the ProSLIC. The PLL_MULT is used to control the
internal PLL, which multiplies PCLK as needed to
generate 16.384 MHz rate needed to run the internal
filters and other circuitry.
The PLL clock synthesizer settles very quickly following
powerup. However, the settling time depends on the
PCLK frequency, and it can be approximately predicted
by the following equation:
For 600 + 1 µF, RZREF = 12 kΩ and C3, C4 = 100 nF.
For 900 + 2.16 µF, RZREF = 12 kΩ and C3, C4 = 220 nF.
to TIP
to RING
Figure 23. R
ZREF
C3
C4
T
SETTLE
External Resistor Placement
ZREF
R
ZREF
R8
, which is inserted into the
R9
=
---------------- -
F
PCLK
64
STIPAC
SRINGAC
Si3215