SI3230MPPQX-EVB Silicon Laboratories Inc, SI3230MPPQX-EVB Datasheet - Page 96

• Manufacturer Part Number: SI3230MPPQX-EVB
• Description: BOARD EVAL W/DISCRETE INTERFACE
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3230MPPQX-EVB

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: Si3230
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si3230
4.4. SLIC Control
See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values
are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
96
Addr. D15
*Note: Si3230 only.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
and written but should be written to zeroes.
Addr.
28
29
30
D14
Loop Closure Threshold.
Loop closure detection threshold. This register defines the upper bounds threshold if hys-
teresis is enabled (direct Register 108, bit 0). The range is 0–80 mA in 1.27 mA steps.
See "2.1.6. Loop Closure Detection" on page 22.
Ring Trip Threshold.
Ring trip detection threshold during ringing. See "2.4.6. Ring Trip Detection" on page 31.
Common Mode Minimum Threshold for Speed-Up.
This register defines the negative common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
D13
Table 38. SLIC Control Indirect Registers Description
Table 37. SLIC Control Indirect Registers Summary
LCRTL[5:0]
D12
RPTP[5:0]
LCRT[5:0]
VMIND[3:0]*
PPT12[7:0]
PPT34[7:0]
PPT56[7:0]
VCMR[3:0]
D11
D10
CMH[5:0]
CML[5:0]
NCLR[12:0]
NRTP[12:0]
NQ12[12:0]
NQ34[12:0]
NQ56[12:0]
Preliminary Rev. 0.96
D9
Description
D8
D7
D6
D5
D4
D3
D2
D1
D0