SI3230MPPQX-EVB Silicon Laboratories Inc, SI3230MPPQX-EVB Datasheet

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SI3230MPPQX-EVB

Manufacturer Part Number
SI3230MPPQX-EVB
Description
BOARD EVAL W/DISCRETE INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheet

Specifications of SI3230MPPQX-EVB

Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3230
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
P
R
Features
Applications
Description
The Si3230 ProSLIC
subscriber line interface ideal for customer premise equipment (CPE) applications.
The ProSLIC integrates subscriber line interface circuit (SLIC) and battery generation
functionality into a single CMOS integrated circuit. The integrated battery supply
continuously adapts its output voltage to minimize power and enables the entire
solution to be powered from a single 3.3 V (Si3230M only) or 5 V supply. The ProSLIC
controls the phone line through Silicon Labs’ Si3201 Linefeed IC or discrete circuitry.
Si3230 features include software-configurable 5 REN internal ringing up to 90 V
DTMF generation and decoding, and a comprehensive set of telephony signaling
capabilities for operation with only one hardware solution. The ProSLIC is packaged in
a 38-pin QFN or TSSOP, and the Si3201 is packaged in a thermally-enhanced 16-pin
SOIC.
Functional Block Diagram
Preliminary Rev. 0.96 7/05
R O
Software Programmable SLIC with
codec interface
Software programmable internal
balanced ringing up to 90 V
(5 REN up to 4 kft, 3 REN up to 8 kft)
Integrated battery supply with dynamic
voltage output
Software programmable linefeed
parameters:
Interface to Broadcom devices
I N G I N G
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
minimizes power in all operating modes
single 3.3 V or 5 V supply
and waveshape
filtering
On-chip dc-dc converter continuously
Entire solution can be powered from a
3.3 V to 35 V dc input range
Dynamic 0 V to –94.5 V output
Ringing frequency, amplitude, cadence,
2-wire ac impedance
constant current feed (20 to 41 mA)
Loop closure and ring trip thresholds and
BCM11xx residential gateway
BCM3341 VOIP processor
BCM33xx cable modem
SLIC
FSYNC
PCLK
SCLK
SDO
SDI
CS
INT
/ B
®
RESET
®
is a low-voltage CMOS device that provides a multi-functional
A T T E R Y
Tone Generators
Impedance Synth
Pulse Metering
DTMF Decoder
FSK Caller ID
P
R O G R A M M A B L E
PK
DC–DC Converter Controller
Si3230
Ring Trip Detect Line
Loop Closure Detect
Ringing Generator
Linefeed Control
Linefeed Monitor
Copyright © 2005 by Silicon Laboratories
Diagnostics
V
SLIC
O L TA G E
Software programmable signal
generation and audio processing:
Extensive test and diagnostic
features
SPI control interface
Extensive programmable interrupts
100% software configurable global
solution
Lead-Free and RoHS-compliant
package options available
Voice over IP
Terminal adapters
Fixed cellular terminal
generation
generation
DTMF generation and decoding
12 kHz/16 kHz pulse metering
Phase-continuous FSK (caller ID)
Dual audio tone generators
Smooth and abrupt polarity reversal
Realtime dc linefeed measurement
GR-909 line test capabilities
Linefeed
Interface
Battery
CMOS SLIC
G
Tip
Ring
E N E R A T I O N
PK
,
Patents pending
U.S. Patent #6,567,521
U.S. Patent #6,812,744
Other patents pending
SRINGDC
STIPDC
FSYNC
RESET
QGND
CAPM
SDCH
SDCL
CAPP
V
IREF
NC
DDA1
Ordering Information
Pin Assignments
10
11
12 13
1
2
3
4
5
6
7
8
9
W I T H
See page 103.
QFN Package
38
14
37
Si3230
15 16 17 18 19
36
35
34 33 32
31
30
29
28
27
26
25
24
23
22
21
20
SDITHRU
DCDRV
ITIPN
IRINGP
IGMP
DCFF
TEST1
GNDD
VDDD
ITIPP
V
IRINGN
DDA2
Si3230

Related parts for SI3230MPPQX-EVB

SI3230MPPQX-EVB Summary of contents

Page 1

P SLIC Features Software Programmable SLIC with codec interface Software ...

Page 2

Si3230 2 Preliminary Rev. 0.96 ...

Page 3

Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Si3230 1. Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information Parameter DC Supply Voltage Input Current, Digital Input Pins Digital Input Voltage ESD, Human Body Model 2 Operating Temperature Range Storage Temperature Range TSSOP-38 Thermal Resistance, Typical QFN-38 ...

Page 5

Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3230 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply ...

Page 6

Si3230 Table 3. AC Characteristics (Continued 3. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Longitudinal to Metallic Balance Metallic to Longitudinal Balance Longitudinal Impedance ...

Page 7

Fundamental Output Power (dBm0) Figure 1. Overload Compression Performance Table 4. Linefeed Characteristics ( 3. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Symbol Loop Resistance ...

Page 8

Si3230 Table 4. Linefeed Characteristics (Continued 3. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Symbol Trapezoidal Ring Crest Factor Accuracy Sinusoidal Ring Crest R ...

Page 9

Table 7. Si3230 DC Characteristics 3. 3. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Symbol High Level Input Voltage V IH Low Level Input ...

Page 10

Si3230 Table 8. Power Supply Characteristics (Continued 3. 5. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Symbol 3 V Supply Current BAT Notes ...

Page 11

Table 10. Switching Characteristics—SPI 3. 70°C for K-Grade, –40 to 85°C for B-Grade, C DDA DDA A Parameter Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK Delay Time, ...

Page 12

Si3230 4.7µF 1 TIP C5 22nF C6 22nF 3 RING Notes: 1. Values and configurations for these components can be derived from Table 16 or from App Note 45. 2. Only one component per system R21 needed All ...

Page 13

SDCH SDCL DCFF DCDRV Notes: 1. Values and configurations for these components can be derived from Table 17 or from App Note 45. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 4. Si3230 DC-DC Converter ...

Page 14

Si3230 SDCH SDCL DCFF DCDRV Figure 5. Si3230M MOSFET/Transformer DC-DC Converter Circuit Table 13. Si3230M MOSFET/Transformer DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C14* C25* C27 470 pF, 100 V, X7R, ±20% R17 R18 1/4 ...

Page 15

Q1 5401 R10 TIP Q6 5551 C8 C5 220nF 22nF R6 C6 80.6 22nF RING Notes: 1. Values and configurations for these components can be derived from Table 16 or from App Note 45. 2. Only one component per system ...

Page 16

Si3230 VINp TX gain = 0.6622 CMlevel VINm VOUTm VOUTp RX gain = 1.2346 Figure 7. Interface to Broadcom BCM11xx Table 15. External Component Values—BCM11xx Interface Component C1 0.1 µ Y5V, ±20% C5, C6 0.1 µF, 100 V, ...

Page 17

Table 16. Component Value Selection for Si3230 Component R28 1/ resistor For V DD For V DD R29 1/ resistor For V CLAMP For V CLAMP For V CLAMP Table 17. Component Value Selection Examples for ...

Page 18

Si3230 2. Functional Description The Si3230 ProSLIC ® single low-voltage CMOS device that provides all the SLIC, DTMF detection, and signal generation functions needed for a complete analog telephone interface when connected to an external codec. The ProSLIC ...

Page 19

R R provide access to these measuring points. The BAT sense circuitry is calibrated on-chip to guarantee measurement accuracy with component tolerances. See Calibration" on page 23 for details. 2.1.3. Linefeed Operation States The ...

Page 20

Si3230 Table 21. Measured Realtime Linefeed Interface Characteristics Parameter Loop Voltage Sense (V – TIP V ) RING Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense BAT Battery Voltage Sense ...

Page 21

Table 22. Associated Power Monitoring and Power Fault Registers Parameter Power Monitor Pointer Line Power Monitor Output Power Alarm Threshold, Q1 & Q2 Power Alarm Threshold, Q3 & Q4 Power Alarm Threshold, Q5 & Q6 Thermal LPF Pole, Q1 & ...

Page 22

Si3230 LCS Input ISP_OUT Signal LVS Processor LFS LCVE 2.1.6. Loop Closure Detection A loop closure event signals that the terminal equipment has gone off-hook during on-hook transmission or on- hook active states. The ProSLIC performs loop closure detection digitally ...

Page 23

Linefeed Calibration An internal calibration algorithm corrects for internal and external component errors. The calibration is initiated by setting the CAL bit in direct Register 96. Upon completion of the calibration cycle, this bit is automatically reset ...

Page 24

Si3230 voltage to the dc-dc converter external circuitry overload condition is detected, the PWM controller will turn off the switching transistor for the remainder of a PWM period to prevent damage components important that the proper ...

Page 25

Constant I Region V BATL TRACK=0 V Figure 10. V Table 24. Associated Relevant DC-DC Converter Registers Parameter DC-DC Converter Power-off Control DC-DC Converter Calibration Enable/Status DC-DC Converter PWM Period DC-DC Converter Min. Off Time High Battery Voltage—V BATH Low ...

Page 26

Si3230 2.2.5. DC-DC Converter Enhancements There are two enhancements to the dc-dc converter. The first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. This option is enabled by setting DCSU ...

Page 27

Oscillator Frequency and Amplitude Each of the two tone generators contains a two-pole resonate oscillator circuit with frequency and amplitude, which are programmed via indirect registers OSC1, OSC1X, OSC1Y, OSC2, OSC2X, and OSC2Y. The sample rate for the two ...

Page 28

Si3230 Table 25. Associated Tone Generator Registers Parameter Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 initial phase coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control Parameter Oscillator 2 Frequency Coefficient Oscillator 2 Amplitude ...

Page 29

Enhanced FSK Waveform Generation Silicon revisions C and higher support enhanced FSK generation capabilities, which can be enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REN = 1 (direct Register 32, bit 6). In this ...

Page 30

Si3230 Table 26. Registers for Ringing Generation (Continued) Ringing frequency Ringing amplitude Ringing initial phase Common Mode Bias Adjust During Ringing Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is ...

Page 31

T 1 ---------- - t = – ⎝ RISE 4 CF where T = ringing ...

Page 32

Si3230 ringing state as indicated by the Linefeed Shadow register (direct Register 64). The data then feeds into a programmable digital low pass filter, which removes unwanted ac signal components before threshold detection. The output of the low pass filter ...

Page 33

Table 28. Recommended Ring Trip Values for Ringing Ringing NRTP Frequency Hz decimal 16.667 64 20 100 30 112 40 128 50 213 60 256 2.5. Pulse Metering Generation There is an additional tone generator suitable for generating tones above ...

Page 34

Si3230 The pulse metering oscillator has a volume envelope (linear ramp) on the on/off transitions of the oscillator. The volume value is incremented by the value in the PLSD register (indirect Register 23 kHz rate. The sinusoidal ...

Page 35

Preliminary Rev. 0.96 Si3230 35 ...

Page 36

Si3230 2.7. Two-Wire Impedance Matching The ProSLIC provides on-chip programmable two-wire impedance settings to meet a wide variety of worldwide two-wire return loss requirements. The two-wire impedance is programmed by loading one of the eight available impedance values into the ...

Page 37

Serial Peripheral Interface The control interface to the ProSLIC is a 4-wire interface modeled after commonly available micro-controller and serial peripheral devices. The interface consists of a clock (SCLK), chip select (CS), serial data input (SDI), and serial data ...

Page 38

Si3230 SCLK CS SDI SDO High Impedance 38 Don't Care Figure 18. Serial Read 8-Bit Mode Preliminary Rev. 0.96 Don't Care ...

Page 39

SDO CPU CS SDI Chip Select Byte SCLK SDI0 SDI1 – SDI2 – – SDI3 – – – C7 ...

Page 40

Si3230 3. Control Registers Note: Any register not listed here is reserved and must not be written. Register Name 0 SPI Mode Select 9 Audio Gain Control 10 Two-Wire Impedance Synthesis Control 11 Hybrid Control 14 Power Down Control 1 ...

Page 41

Table 30. Direct Register Summary (Continued) Register Name 37 Oscillator 1 Active Timer—High Byte 38 Oscillator 1 Inactive Timer—Low Byte 39 Oscillator 1 Inactive Timer—High Byte 40 Oscillator 2 Active Timer—Low Byte 41 Oscillator 2 Active Timer—High Byte 42 Oscillator ...

Page 42

Si3230 Table 30. Direct Register Summary (Continued) Register Name 66 Battery Feed Control 67 Automatic/Manual Control 68 Loop Closure/Ring Trip Detect Status 69 Loop Closure Debounce Interval 70 Ring Trip Detect Debounce Interval 71 Loop Current Limit 72 On-Hook Line ...

Page 43

Table 30. Direct Register Summary (Continued) Register Name 94 PWM Pulse Width 95 Reserved 96 Calibration Control/ Status Register 1 97 Calibration Control/ Status Register 2 98 RING Gain Mismatch Calibration Result 99 TIP Gain Mismatch Calibration Result 100 Differential ...

Page 44

Si3230 Register 0. SPI Mode Select Bit D7 D6 Name SPIDC SPIM Type R/W R/W Reset settings = 00xx_xxxx Bit Name 7 SPIDC SPI Daisy Chain Mode Enable Disable SPI daisy chain mode Enable SPI daisy ...

Page 45

Register 9. Audio Gain Control Bit D7 D6 Name RXHP TXHP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 RXHP Receive Path High Pass Filter Disable HPF enabled in receive path, RHDF HPF bypassed ...

Page 46

Si3230 Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation Off ...

Page 47

Register 11. Hybrid Control Bit D7 D6 Name HYBP[2:0] Type Reset settings = 0011_0011 Bit Name 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 ...

Page 48

Si3230 Register 14. Power Down Control 1 Bit D7 D6 Name PMON Type Reset settings = 0001_0000 Bit D7 D6 Name PMON Type Reset settings = 0001_0000 Bit Name 7:6 Reserved Read returns zero. 5 PMON Pulse Metering DAC Power-On ...

Page 49

Register 15. Power Down Control 2 Bit D7 D6 Name ADCM Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 ADCM Analog to Digital Converter Manual/Automatic Power Control Automatic power control Manual ...

Page 50

Si3230 Register 18. Interrupt Status 1 Bit D7 D6 Name PMIP PMAP RGIP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIP Pulse Metering Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 ...

Page 51

Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Q4AP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...

Page 52

Si3230 Register 20. Interrupt Status 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 CMCP Common Mode Calibration Error Interrupt. This bit ...

Page 53

Register 21. Interrupt Enable 1 Bit D7 D6 Name PMIE PMAE RGIE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIE Pulse Metering Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. 6 PMAE Pulse ...

Page 54

Si3230 Register 22. Interrupt Enable 2 Bit D7 D6 Name Q6AE Q5AE Q4AE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AE Power Alarm Q6 Interrupt Enable Interrupt masked Interrupt enabled. 6 Q5AE Power ...

Page 55

Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 CMCE Common Mode Calibration Error Interrupt Enable Interrupt masked Interrupt enabled. 1 INDE Indirect ...

Page 56

Si3230 Register 24. DTMF Decode Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 VAL DTMF Valid Digit Decoded Not currently detecting digit Currently detecting digit. 3:0 ...

Page 57

Register 28. Indirect Data Access—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA into ...

Page 58

Si3230 Register 30. Indirect Address Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect ...

Page 59

Register 32. Oscillator 1 Control Bit D7 D6 Name OSS1 REL Type R R/W Reset settings = 0000_0000 Bit Name 7 OSS1 Oscillator 1 Signal Status Output signal inactive Output signal active. 6 REL Oscillator 1 ...

Page 60

Si3230 Register 33. Oscillator 2 Control Bit D7 D6 Name OSS2 Type R Reset settings = 0000_0000 Bit Name 7 OSS2 Oscillator 2 Signal Status Output signal inactive Output signal active. 6 Reserved Read returns zero. ...

Page 61

Register 34. Ringing Oscillator Control Bit D7 D6 Name RSS RDAC Type R Reset settings = 0000_0000 Bit Name 7 RSS Ringing Signal Status Ringing oscillator output signal inactive Ringing oscillator output signal active. 6 Reserved ...

Page 62

Si3230 Register 35. Pulse Metering Oscillator Control Bit D7 D6 Name PSTAT Type R Reset settings = 0000_0000 Bit Name 7 PSTAT Pulse Metering Signal Status Output signal inactive Output signal active. 6:5 Reserved Read returns ...

Page 63

Register 36. Oscillator 1 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 µs Register 37. Oscillator 1 Active Timer—High Byte Bit D7 D6 Name Type ...

Page 64

Si3230 Register 39. Oscillator 1 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT1[15:8] Oscillator 1 Inactive Timer. Register 40. Oscillator 2 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = ...

Page 65

Register 42. Oscillator 2 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 µs Register 43. Oscillator 2 Inactive Timer—High Byte Bit D7 D6 Name Type ...

Page 66

Si3230 Register 45. Pulse Metering Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 PAT[15:8] Pulse Metering Active Timer. Register 46. Pulse Metering Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset ...

Page 67

Register 48. Ringing Oscillator Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[7:0] Ringing Active Timer. LSB = 125 µs Register 49. Ringing Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset ...

Page 68

Si3230 Register 51. Ringing Oscillator Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RIT[15:8] Ringing Inactive Timer. Register 52. FSK Data Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 ...

Page 69

Register 64. Linefeed Control Bit D7 D6 Name LFS[2:0] Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual realtime linefeed state. Automatic operations may cause actual linefeed state ...

Page 70

Si3230 Register 65. External Bipolar Transistor Control Bit D7 D6 Name SQH Type R/W Reset settings = 0110_0001 Bit Name 7 Reserved Read returns zero. 6 SQH Audio Squelch squelch STIPAC and SRINGAC pins squelched. ...

Page 71

Register 66. Battery Feed Control Bit D7 D6 Name Type Reset settings = 0000_0011 Bit Name 7:5 Reserved Read returns zero. 4 VOV Overhead Voltage Range Increase. This bit selects the programmable range for ...

Page 72

Si3230 Register 67. Automatic/Manual Control Bit D7 D6 Name MNCM MNDIF Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 MNCM Common Mode Manual/Automatic Select Automatic control Manual control, in which ...

Page 73

Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the realtime output of ring ...

Page 74

Si3230 Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 Name Type Reset settings = 0000_1010 Bit Name 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum ...

Page 75

Register 72. On-Hook Line Voltage Bit D7 D6 Name VSGN Type R/W Reset settings = 0010_0000 Bit Name 7 Reserved Read returns zero. 6 VSGN On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage polarity ...

Page 76

Si3230 Register 74. High Battery Voltage Bit D7 D6 Name Type Reset settings = 0011_0010 Bit Name 7:6 Reserved Read returns zero. 5:0 VBATH[5:0] High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be ...

Page 77

Register 76. Power Monitor Pointer Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 PWRMP[2:0] Power Monitor Pointer. Selects the external transistor from which to read power output. The power of the ...

Page 78

Si3230 Register 78. Loop Voltage Sense Bit D7 D6 Name LVSP Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 LVSP Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage ...

Page 79

Register 80. TIP Voltage Sense Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the realtime voltage at TIP with respect to ground. The range (0x00) to ...

Page 80

Si3230 Register 83. Battery Voltage Sense 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the realtime voltage ground. ...

Page 81

Register 86. Transistor 3 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Transistor 3 Current Sense. This register reports the realtime current through Q3. The range (0x00) to 9.59 mA ...

Page 82

Si3230 Register 89. Transistor 6 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Transistor 6 Current Sense. This register reports the realtime current through Q6. The range (0x00) to 80.58 ...

Page 83

Register 93. DC-DC Converter Switching Delay Bit D7 D6 Name DCCAL DCPOL Type R/W Reset settings = 0001_0100 Bit Name 7 DCCAL DC-DC Converter Peak Current Monitor Calibration Status (Si3230 only). Writing a one to this bit starts the dc-dc ...

Page 84

Si3230 Register 94. DC-DC Converter PWM Pulse Width Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DCPW[7:0] DC-DC Converter Pulse Width. Pulse width of DCDRV is given (DCPW – DCTOF – 4) 61.035 ...

Page 85

Register 96. Calibration Control/Status Register 1 Bit D7 D6 Name CAL CALSP Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 CAL Calibration Control/Status Bit. Setting this bit begins calibration of the entire system. 0 ...

Page 86

Si3230 Register 97. Calibration Control/Status Register 2 Bit D7 D6 Name Type Reset settings = 0001_1111 Bit Name 7:5 Reserved Read returns zero. 4 CALM1 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled ...

Page 87

Register 98. RING Gain Mismatch Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current. Register 99. TIP Gain Mismatch Calibration ...

Page 88

Si3230 Register 101. Common Mode Loop Current Gain Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0001 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGC[4:0] Common Mode DAC Gain Calibration Result. Register 102. Current Limit Calibration Result ...

Page 89

Register 104. Analog DAC/ADC Offset Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3 DACP Positive Analog DAC Offset. 2 DACN Negative Analog DAC Offset. 1 ADCP Positive Analog ADC Offset. 0 ...

Page 90

Si3230 Register 107. DC Peak Current Monitor Calibration Result Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:4 Reserved Read returns zero. 3:0 CMDCPK[3:0] DC Peak Current Monitor Calibration Result. Register 108. Enhancement Enable Bit D7 D6 ...

Page 91

Bit Name 4 ZSEXT Impedance Internal Reference Resistor Disable. When enabled, this bit removes the internal reference resistor used to synthesize ac impedances for 600 + 2.1 µF and 900 + 2.16 µF so that an external resistor reference may ...

Page 92

Si3230 4. Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect ...

Page 93

Table 32. DTMF Indirect Registers Description (Continued) Addr. 2 DTMF Row 2 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 2 DTMF detection. If the ratio of power in row 2 to total ...

Page 94

Si3230 4.2. Oscillators See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. ...

Page 95

Table 34. Oscillator Indirect Registers Description (Continued) Addr. 20 Ringing Oscillator Frequency Coefficient. Sets ringing generator frequency. 21 Ringing Oscillator Amplitude Register. Sets ringing generator signal amplitude. 22 Ringing Oscillator Initial Phase Register. Sets initial phase of ringing generator signal. ...

Page 96

Si3230 4.4. SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas ...

Page 97

Table 38. SLIC Control Indirect Registers Description (Continued) Addr. 31 Common Mode Maximum Threshold for Speed-Up. This register defines the positive common mode voltage threshold. Exceeding this threshold enables a wider bandwidth of dc linefeed control for faster settling times. ...

Page 98

Si3230 Table 40. FSK Control Indirect Registers Description Addr. 99 FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener- ating a space or “0”. When the ...

Page 99

Pin Descriptions: Si3230 FSYNC 2 RESET 3 SDCH 4 SDCL DDA1 IREF 7 CAPP 8 QGND 9 CAPM 10 STIPDC 11 SRINGDC Pin # Pin # Name QFN TSSOP ...

Page 100

Si3230 Pin # Pin # Name QFN TSSOP 5 9 SDCL DC Monitor. DC-DC converter monitor input used to detect overcurrent situations in the con- verter VDDA1 Analog Supply Voltage. Analog power supply for internal analog circuitry. 7 ...

Page 101

Pin # Pin # Name QFN TSSOP 23 27 VDDA2 Analog Supply Voltage. Analog power supply for internal analog circuitry ITIPP Positive TIP Current Control. Analog current output driving Q1 ITIPN Negative TIP Current Control. Analog ...

Page 102

Si3230 6. Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I — 3 RING I/O 4 VBAT — 5 VBATH — 7 GND — 8 VDD — 10 SRINGE O 11 STIPE O ...

Page 103

... Line Interface Si3201-BS Line Interface Notes: 1. “X” denotes product revision. 2. Add an “R” at the end of the device to denote tape and reel options; 2500 quantity per reel. Item Si3230PPQX-EVB Si3230PPQ1-EVB Si3230MPPQX-EVB Si3230MPPQ1-EVB Si3230DCQX-EVB Si3230DCQ1-EVB DCFF Pin Package Output DCDRV QFN-38 DCDRV ...

Page 104

Si3230 8. Package Outline: 38-Pin QFN Figure 20 illustrates the package details for the Si3230. Table 41 lists the values for the dimensions shown in the illustration. Figure 20. 38-Pin Quad Flat No-Lead Package (QFN) Table 41. Package Diagram Dimensions ...

Page 105

Package Outline: 38-Pin TSSOP Figure 21 illustrates the package details for the Si3230. Table 42 lists the values for the dimensions shown in the illustration. E/2 2x ddd aaa C Seating Plane C Figure ...

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Si3230 10. Package Outline: 16-Pin SOIC Figure 22 illustrates the package details for the Si3201. Table 43 lists the values for the dimensions shown in the illustration . –A– ...

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OCUMENT HANGE IST Revision 0.2 to Revision 0.9 Updated Table 1 on page 4. Added QFN thermal resistance Updated Table 10 on page 11. Added Delay Time between Chip Selects, t continuous SCLK. Updated Table 38 on ...

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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...

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