LM5069EVAL/NOPB National Semiconductor, LM5069EVAL/NOPB Datasheet - Page 3

• Manufacturer Part Number: LM5069EVAL/NOPB
• Description: BOARD EVALUATION LM5069
• Manufacturer: National Semiconductor

Specifications of LM5069EVAL/NOPB

• Main Purpose: Power Management, Hot Swap Controller
• Utilized Ic / Part: LM5069
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: LM5069EVAL

The PGD logic level output is low during turn-on, and switches
high when the output voltage at OUT has increased to within
1.25V of the input voltage, signifying the turn-on procedure is
essentially complete. If the OUT voltage decreases more than
2.5V below VIN due to a fault, PGD switches low. The high
level voltage at PGD can be any appropriate voltage up to
+80V, and can be higher or lower than the voltages at VIN
and OUT.
Board Layout and Probing Cautions
The pictorial in Figure 1 shows the placement of the circuit
components. The following should be kept in mind when the
board is powered:
1.
2.
High voltage, equal to VIN, is present on C3, C4, C7, Q1,
and various points within the circuit. Use CAUTION when
probing the circuit to prevent injury, as well as possible
damage to the circuit.
At maximum load current (5.5A), the wire size and length
used to connect the power source and the load become
important. The wires connecting this evaluation board to
the power source SHOULD BE TWISTED TOGETHER
to minimize inductance in those leads. The same applies
for the wires connecting this board to the load. This
recommendation is made in order to minimize high
voltage transients from occuring when the load current is
shut off.
FIGURE 3. Power Up Using Power Limit and Current Limit
3
The UVLO and OVLO thresholds are set by resistors R1-R3.
The UVLO and OVLO thresholds are reached when the volt-
age at the UVLO and OVLO pins each reach 2.5V, respec-
tively. The internal 21µA current sources provide hysteresis
for each of the thresholds.
Board Connections/Startup
The input voltage source is connected to the J1 connector,
and the load is connected to the J2 connector at the OUT and
GND terminals. USE TWISTED WIRES. A voltmeter should
be connected to the input terminals, and one to the output
terminals. The input current can be monitored with an amme-
ter or current probe. To monitor the status of the PGD output,
connect a voltmeter from PGOOD to GND on the J2 terminal
block. Put the toggle switch in the ON position.
Increase the input voltage gradually. The input current should
remain less than 2 mA until the upper UVLO threshold is
reached (
turned on as described in the Theory of Operation section. If
viewed on an oscilloscope, the input current increases as
shown in Figure 3 before settling at the value defined by the
load. The turn-on timing depends on the input voltage, power
limit setting, current limit setting, and the final load current,
and is between
with a 4A load current, with VIN = 36V. See Figures 9 and 10.
≊
34.4V). When the threshold is reached, Q1 is
≊
3.0 ms with no load current, and
20205303
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≊
7.5 ms