EZ80L920210ZCO Zilog, EZ80L920210ZCO Datasheet - Page 59

• Manufacturer Part Number: EZ80L920210ZCO
• Description: KIT DEV EZ80 WEB SERVER
• Manufacturer: Zilog
• Series: eZ80®r

Specifications of EZ80L920210ZCO

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: eZ80L92
• Primary Attributes: *
• Secondary Attributes: *
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3165; EZ80L920210ZCO; Q1370684

UM012906-0103
The EMAC can be additionally protected by placing an ESD protection
array on the module at U9. This array can be either of the LCDA15C-6
(Semtech) or ESDA25B1 (ST Microelectronics) devices.
GPIO Pins for Enabling LAN Activity, Sleep, Interrupt
GPIO input bit PD4 serves as an active High interrupt input for the
EMAC’s INTRQ0 output.
GPIO output bit PD7 can be used to enter the EMAC into SLEEP mode.
When pulling SLEEP (PD7) Low after enabling HWStandbyE and
HWSleepE modes, the chip draws lower current, because only the
receiver is operating. A zero-Ohm resistor at position R14 on the
eZ80L92 Development Kit is required for this function.
If LAN activity is detected, the LANACT signal is pulled Low. The
LANACT is connected to GPIO input PD6 and can be used in interrupt
edge-detection mode to wake up and reinitialize the Ethernet chip. A
zero-Ohm resistor at position R15 on the module is required for this func-
tion. In this case, the PD6 pin is not available for GPIO on the I/O con-
nector.
EMAC Ports
Chip Select CS3 is used for selecting the EMAC device. The base address
is user-selectable. The EMAC is connected as an 8-bit device.
EMAC Wait States
The CS8900A EMAC should be operated in Intel bus mode so that the
setup and hold times for the I/O access are met. For 48MHz operation,
first set CS3_BMC (I/O address
system clock cycles per bus cycle) and then CS3_CTL (I/O Address
to
READ and WRITE access time is:
18h
2 x 4 x 20.8ns–16ns (for capacitive and chip delays) = 150ns
(0 wait states for I/O). For a 20.8ns CPU Clock cycle time, the
PRELIMINARY
F3h
) to
eZ80L92 Development Kit
84h
(Intel bus mode with four
Operational Description
User Manual
B3h
)
49