CDB42528 Cirrus Logic Inc, CDB42528 Datasheet - Page 47

• Manufacturer Part Number: CDB42528
• Description: BOARD EVAL FOR CS42528/CS49300
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42528

• Main Purpose: Audio, Audio Processing
• Embedded: Yes, DSP
• Utilized Ic / Part: CS49300, CS42528
• Primary Attributes: 8 Single-Ended Analog Inputs and Outputs, 4 S/PDIF Inputs and 2 S/PDIF Outputs
• Secondary Attributes: Parallel, RS422, RS232, UDSP Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1503

DS586F1
6.3
6.3.1
6.3.2
6.3.3
6.3.4
PDN_RCVR1 PDN_RCVR0
7
Power Control (address 02h)
POWER DOWN RECEIVER (PDN_RCVRX)
POWER DOWN ADC (PDN_ADC)
POWER DOWN DAC PAIRS (PDN_DACX)
POWER DOWN (PDN)
Default = 10
00 - Receiver and PLL in normal operational mode.
01 - Receiver and PLL held in a reset state. Equivalent to setting 11.
10 - Reserved.
11 - Receiver and PLL held in a reset state. Equivalent to setting 01.
Function:
Default = 0
Function:
Default = 0
Function:
Default = 1
Function:
Places the S/PDIF receiver and PLL in a reset state. It is advised that any change of these bits be
made while the DACs are muted or the power-down bit (PDN) is enabled to eliminate the possibility
of audible artifacts.
It should be noted that, for Revision C compatibility, PDN_RCVR1 may be set to ‘0’ and receiver op-
eration may be controlled with the PDN_RCVR0 bit.
When enabled the stereo analog to digital converter will remain in a reset state. It is advised that any
change of this bit be made while the DACs are muted or the power-down bit (PDN) is enabled to elim-
inate the possibility of audible artifacts.
When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state.
The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation can occur.
6
PDN_ADC
5
PDN_DAC4
4
PDN_DAC3
3
PDN_DAC2
2
PDN_DAC1
1
CS42528
PDN
0
47