CDB42518 Cirrus Logic Inc, CDB42518 Datasheet - Page 6

• Manufacturer Part Number: CDB42518
• Description: BOARD EVAL FOR CS42518 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42518

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42518/16
• Primary Attributes: 6 Single-Ended Analog Inputs and 8 Outputs, S/PDIF Digital Audio Transmitter and Receiver
• Secondary Attributes: GUI, I2C, SPI Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1502

CS42518
LIST OF TABLES
Table 1. Common OMCK Clock Frequencies ............................................................................................ 26
Table 2. Common PLL Output Clock Frequencies..................................................................................... 26
Table 3. Slave Mode Clock Ratios ............................................................................................................. 27
Table 4. Serial Audio Port Channel Allocations ......................................................................................... 28
Table 5. DAC De-Emphasis ....................................................................................................................... 49
Table 6. Receiver De-Emphasis ................................................................................................................ 49
Table 7. Digital Interface Formats .............................................................................................................. 50
Table 8. ADC One-Line Mode.................................................................................................................... 50
Table 9. DAC One-Line Mode.................................................................................................................... 50
Table 10. RMCK Divider Settings .............................................................................................................. 53
Table 11. OMCK Frequency Settings ........................................................................................................ 53
Table 12. Master Clock Source Select....................................................................................................... 54
Table 13. AES Format Detection ............................................................................................................... 55
Table 14. Receiver Clock Frequency Detection......................................................................................... 56
Table 15. Example Digital Volume Settings ............................................................................................... 58
Table 16. ATAPI Decode ........................................................................................................................... 60
Table 17. Example ADC Input Gain Settings ............................................................................................. 61
Table 18. TXP Output Selection................................................................................................................. 63
Table 19. Receiver Input Selection ............................................................................................................ 63
Table 20. Auxiliary Data Width Selection ................................................................................................... 66
Table 21. External PLL Component Values & Locking Modes .................................................................. 77
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DS584F1