CDB42518 Cirrus Logic Inc, CDB42518 Datasheet - Page 48

• Manufacturer Part Number: CDB42518
• Description: BOARD EVAL FOR CS42518 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42518

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42518/16
• Primary Attributes: 6 Single-Ended Analog Inputs and 8 Outputs, S/PDIF Digital Audio Transmitter and Receiver
• Secondary Attributes: GUI, I2C, SPI Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1502

48
6.4
6.4.1
6.4.2
6.4.3
6.4.4
CODEC_FM1 CODEC_FM0
7
Functional Mode (address 03h)
CODEC FUNCTIONAL MODE (CODEC_FMX)
SERIAL AUDIO INTERFACE FUNCTIONAL MODE (SAI_FMX)
ADC SERIAL PORT SELECT (ADC_SP SELX)
DAC DE-EMPHASIS CONTROL (DAC_DEM)
Selects the required range of sample rates for all converters clocked from the Codec serial port
(CODEC_SP). Bits must be set to the corresponding sample rate range when the CODEC_SP is in Master
or Slave Mode.
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 192 kHz sample rates)
11 - Reserved
Function:
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 192 kHz sample rates)
11 - Reserved
Function:
Default = 00
00 - Serial data on CX_SDOUT pin, clocked from the CODEC_SP. S/PDIF data on SAI_SDOUT pin.
01 - Serial data on CX_SDOUT pin, clocked from the SAI_SP. S/PDIF data on SAI_SDOUT pin.
10 - Serial data on SAI_SDOUT pin, clocked from the SAI_SP. No S/PDIF data available.
11 - Reserved
Function:
Default = 0
Function:
Selects the required range of sample rates for the Serial Audio Interface port (SAI_SP). These bits
must be set to the corresponding sample rate range when the SAI_SP is in Master or Slave Mode.
Selects the desired clocks and routing for the ADC serial output.
Enables the digital filter to maintain the standard 15µs/50µs digital de-emphasis filter response at the
auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless
of this register setting, at any other sample rate. If the FRC_PLL_LK bit is set to a ‘1’b, the auto-detect
sample rate feature is disabled. To apply the correct de-emphasis filter, use the DE-EMPH bits in the
6
SAI_FM1
5
SAI_FM0
4
ADC_SP SEL1 ADC_SP SEL0
3
2
DAC_DEM
1
CS42518
RCVR_DEM
DS584F1
0