D12 ISA PC EVAL KIT NXP Semiconductors, D12 ISA PC EVAL KIT Datasheet - Page 12

• Manufacturer Part Number: D12 ISA PC EVAL KIT
• Description: EVAL KIT FOR PDIUSBD12 USB EPP
• Manufacturer: NXP Semiconductors

Specifications of D12 ISA PC EVAL KIT

• Main Purpose: Interface, USB 2.0 Host/Controller
• Utilized Ic / Part: PDIUSBD12
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: Q2544495

Interconnectivity
PDIUSBD12 Evaluation Board (PC Kit) User’s Manual
Schematics
Schematics for PDIUSBD12 evaluation board
C15
1000P
_______________________________________________________________________________________________
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
ADDR2
ADDR1
ADDR0
-IOW
-IOR
-DACK
-AD_EN
RESET
ADDR2
ADDR1
ADDR0
VCC
INT_EN
INT_N
D7
D6
D5
D4
D3
D2
D1
D0
VCC
J3
CON20A
19
11
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
8
9
J2
DB25
Shell to GND
1
3
5
7
9
11
13
15
17
19
21
23
25
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
1
3
5
7
9
11
13
15
17
19
C1
4.7 TANT
O1
O2
O3
O4
O5
O6
O7
O8
10
12
14
16
18
20
22
24
B1
B2
B3
B4
B5
B6
B7
B8
10
12
14
16
18
20
2
4
6
8
2
4
6
8
18
17
16
15
14
13
12
11
19
18
17
16
15
14
13
12
U2
74LS245
-DIR_245
U5
16L8
CLKOUT
-AD_EN
RESET
-DACK
-RD_EVAL
-WR_EVAL
-CS_D12
ZERO_WAIT
RESET_N
IRQ
CLKOUT
INT_N
RESET_N
-AD_EN
ADDR2
ADDR1
ADDR0
-IOW
-IOR
T/C
DRQ
IRQ
D0
D1
D2
D3
D4
D5
D6
D7
-IOW
-IOR
Philips Semiconductors - Asia Product Innovation Centre
C8
0.1
R4
4.7K
VCC
R5
4.7K
C9
0.1
C10
0.1
-CS_D12
SUSPEND
C11
0.1
INT_N
D0
D1
D2
D3
D4
D5
D6
D7
Visit
470P, Ceramic
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D8
D6
D7
C13
C12
0.1
10
11
12
13
14
18
16
14
12
13
14
17
18
11
1
2
3
4
5
6
7
8
9
9
7
5
3
3
4
7
8
1
http://www.flexiusb.com
U1
U3
74HCT244
U6
74HCT273
DATA0
DATA1
DATA2
DATA3
GND
DATA4
DATA5
DATA6
DATA7
ALE
CS_N
SUSPEND
CLKOUT
INT_N
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
D1
D2
D3
D4
D5
D6
D7
D8
CLK
CLR
V_BUS
BUS POWERED
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
VCC
PDIUSBD12
+
DMACK_N
RESET_N
VOUT3.3
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
S5
1G
2G
DMREQ
C7
10 TANT
XTAL2
XTAL1
EOT_N
2
5
6
9
12
15
16
19
WR_N
GL_N
RD_N
VCC
A0
D+
D-
2
4
6
8
11
13
15
17
1
19
13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
VCC
ADDR0
XTAL2
XTAL1
-DACK
Title
Size
Date:
D1
GREEN
R1
470
DRQ
-IOW
-IOR
U4A
74LS05
U4F
74LS05
A
2
12
D12 EVALUATION BOARD
Document Number
D12-EVAL-200
Thursday, April 23, 1998
C5
47P
Y1 6MHz
V_BUS
R2
22 1%
OSC1
R11
1K
R16
1M
4
1
C3
0.1
C6
22P
* OSC1 is optional replacement
for Y1, C5 and C6.
G
N
3
V
O
R3
22 1%
+
5
8
U4B
74LS05
C2
4.7 TANT
5
V_BUS
VCC
4
U4D
74LS05
R7
10K
Ferrite Bead
U4C
74LS05
9
L2
Sheet
R8
10K
D2
RED
L1
Ferrite Bead
C16
0.1
R12
470
6
R9
10K
11
R10
10K
D3
RED
1
R13
470
8
Page 12 of 14
REV. 2.1
U4E
74LS05
of
C14
0.1
D4
RED
R14
470
10
1
2
3
4
5
J1
UP_CONN
1
VBUS
D-
D+
GND
SHIELD
VCC
D5
RED
Rev
VCC
R15
470
2.00
S1
S2
S3
S4