EVAL-ADM1060EBZ Analog Devices Inc, EVAL-ADM1060EBZ Datasheet
EVAL-ADM1060EBZ
Specifications of EVAL-ADM1060EBZ
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EVAL-ADM1060EBZ Summary of contents
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FEATURES Faults detected on 7 independent supplies 1 high voltage supply ( 14 positive voltage only supplies ( positive/negative voltage supplies (+ and – –6 ...
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ADM1060 TABLE OF CONTENTS General Description ......................................................................... 3 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 7 Typical Performance Characteristics ............................................. 8 Inputs................................................................................................ 11 SFD REGISTER NAMES........................................................... 14 SFD Register Bit Maps ............................................................... 15 Programming .................................................................................. 21 Logic ................................................................................................. 22 PLBA REGISTER BIT ...
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GENERAL DESCRIPTION (continued from Page 1) All of the inputs and outputs described previously are controlled by the programmable logic block array (PLBA). This is the logic core of the ADM1060 comprised of nine macrocells, one for each ...
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ADM1060 ADM1060 HIGH SUPPLY VH 8 (14.4V) FAULT DETECTOR POSITIVE VP1 9 SUPPLY FAULT DETECTOR 1 VP2 10 VP3 11 VP4 POSITIVE 12 SUPPLY FAULT DETECTOR 4 BIPOLAR VB1 13 SUPPLY FAULT DETECTOR 1 BIPOLAR VB2 14 SUPPLY FAULT DETECTOR ...
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SPECIFICATIONS ( 14.4 V, VPn = 3 6.0 V, Table 1. Parameter POWER SUPPLY ARBITRATION VDDCAP POWER SUPPLY Supply Current Additional Current Available 2 from VDDCAP SUPPLY FAULT DETECTORS Input Impedance VH ...
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ADM1060 Parameter 4 DIGITAL INPUTS (GPI 1–4, WDI, A0, A1) Input High Voltage Input Low Voltage Input High Current Input Low Current Input Capacitance Programmable Pull-Down Current, I PULLDOWN SERIAL BUS DIGITAL ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Absolute Maximum Ratings Parameter Voltage on VH Pin, PDO Pins Voltage on VP Pins Voltage on VB Pins Voltage on Any Other Input Input Current at Any Pin Package Input Current Maximum Junction Temperature (T ...
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ADM1060 TYPICAL PERFORMANCE CHARACTERISTICS 6 VP1 (V) VH, VP1 Figure 2. V vs. V and V VDDCAP VH 3.0 2.5 2.0 1.5 1.0 0 ...
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V = 4.75V VDDCAP 0.5% 0. 2.7V VDDCAP –0.5% –1.0% –1.5% –40 –25 – TEMPERATURE (°C) Figure 8. Percent Deviation in V vs. Temperature THRESH 14.0 13.5 13.0 12.5 0µA LOAD 12.0 ...
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ADM1060 110 108 106 104 102 100 –40 –25 – TEMPERATURE (°C) Figure 14. Oscillator Frequency vs. Temperature 6.00 5.75 5.50 V 5.25 5.00 V 4.75 4.50 0 100 200 I (µA) LOAD ...
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INPUTS POWERING THE ADM1060 The ADM1060 is powered from the highest voltage input on either the Positive Only supply inputs (VPn) or the High Volt- age supply input (VH). The same pins are used for supply fault detection (discussed below). ...
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ADM1060 where Voltage Range V ( 1.8 V 0.604 1.204 1.003 1.999 2.005 3.997 4 14.4 V 4.849 9.666 –2 V ...
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SFD FAULT TYPES Three types of faults can be asserted by the SFD fault fault, and an out-of-window fault (where the UV and OV faults are OR’ed together). The type of fault required is programmed using ...
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ADM1060 SFD REGISTER NAMES Table 4. List of Registers for the Supply Fault Detectors Hex Address Table Name A0 Table 5 BS1OVTH A1 Table 6 BS1OVHYST A2 Table 7 BS1UVTH A3 Table 8 BS1UVHYST A4 Table 9 BS1SEL A8 Table ...
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SFD Register Bit Maps BIPOLAR SUPPLY FAIL DETECT (BSn SFD) REGISTERS Table 5. Register 0xA0, 0xA8 BSnOVTH (Power-On Default 0xFF) Bit Name R/W Description 7–0 OV7–OV0 R/W 8-Bit Digital Value for OV Threshold on BSn SFD Table 6. Register 0xA1, ...
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ADM1060 HIGH VOLTAGE SUPPLY FAULT DETECT (HV SFD) REGISTERS Table 10. Register 0xB0 HSOVTH (Power-On Default 0xFF) Bit Name R/W Description 7–0 OV7–OV0 R/W 8-Bit Digital Value for OV Threshold on HV SFD Table 11. Register 0xB1 HSOVHYST (Power-On Default ...
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POSITIVE VOLTAGE SUPPLY FAULT DETECT (PSn SFD) REGISTERS Table 15. Register 0xB8, 0xC0, 0xC8, 0xD0 PSnOVTH (Power-On Default 0xFF) Bit Name R/W Description 7−0 OV7−OV0 R/W 8-Bit Digital Value for OV Thresh- old on PSn SFD. Table 16. Register 0xB9, ...
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ADM1060 WATCHDOG FAULT DETECTOR The ADM1060 has a watchdog fault detector. This can be used to monitor a processor clock to ensure normal operation. The detector monitors the WDI pin, expecting a low-to-high or high-to-low transition within a preprogrammed period. ...
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GENERAL-PURPOSE INPUTS (GPIs) The ADM1060 has four general-purpose logic inputs (GPIs). These are TTL/CMOS logic level compatible. Standard logic signals can be applied to the pins: RESET from reset generators, PWRGOOD signals, fault flags, manual resets, and so on. These ...
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ADM1060 Table 24. Registers for the Pull-Down Current Sources on Logic Inputs Hex Address Name Default Power On Value 91 PDEN 0x00 Table 25. PDEN Register 0x91 Bit Map (Power-On Default 0x00) Bit Name R/W Description 7 Reserved N/A Cannot ...
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PROGRAMMING PROGRAMMABLE LOGIC BLOCK ARRAY The ADM1060 contains a programmable logic block array (PLBA). This block is the logical core of the device. The PLBA (and the PDBs—see the Programmable Delay Block section) provides the sequencing function of the ADM1060. ...
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ADM1060 LOGIC NOT CONNECTED PLB1 PLB2 INVERT 0x00 P1PLBPOLA.0 IGNORE 0x01 P1PLBIMKA.0 PLB3 INVERT 0x00 P1PLBPOLA.1 IGNORE 0x01 P1PLBIMKA.1 PLB4 INVERT 0x00 P1PLBPOLA.2 IGNORE 0x01 P1PLBIMKA.2 PLB5 INVERT 0x00 P1PLBPOLA.3 IGNORE 0x01 P1PLBIMKA.3 PLB6 INVERT 0x00 P1PLBPOLA.4 IGNORE 0x01 P1PLBIMKA.4 ...
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The control bits for these macrocells are stored locally in latches that are loaded at power-up. These latches can also be updated via the serial interface. The registers containing the macrocell control bits and the function of each bit are ...
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ADM1060 Hex Address Table Name 15 Table 34 P2GPIIMK 16 Table 35 P2WDICFG 17 Table 36 PS2EN 18 Table 29 P2PLBPOLB 19 Table 30 P2PLBIMKB 1A Table 31 P2SFDPOLB 1B Table 32 P2SFDIMKB 20 Table 29 P3PLBPOLA 21 Table 30 ...
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Hex Address Table Name 39 Table 30 P4PLBIMKB 3A Table 31 P4SFDPOLB 3B Table 32 P4SFDIMKB 40 Table 29 P5PLBPOLA 41 Table 30 P5PLBIMKA 42 Table 31 P5SFDPOLA 43 Table 32 P5SFDIMKA 44 Table 33 P5GPIPOL 45 Table 34 P5GPIIMK ...
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ADM1060 Hex Address Table Name 61 Table 30 P7PLBIMKA 62 Table 31 P7SFDPOLA 63 Table 32 P7SFDIMKA 64 Table 33 P7GPIPOL 65 Table 34 P7GPIIMK 66 Table 35 P7WDICFG 67 Table 36 PS7EN 68 Table 29 P7PLBPOLB 69 Table 30 ...
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Hex Address Table Name 84 Table 33 P9GPIPOL 85 Table 34 P9GPIIMK 86 Table 35 P9WDICFG 87 Table 36 PS9EN 88 Table 29 P9PLBPOLB 89 Table 30 P9PLBIMKB 8A Table 31 P9SFDPOLB 8B Table 32 P9SFDIMKB Default Power- On Value ...
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ADM1060 PLBA REGISTER BIT MAPS Table 29. PnPLBPOLA/PnPLBPOLB Registers Bit Map (Power-On Default 0x00) Bit Name R/W Description 7–0 POL9−POL1 R/W If high, invert the PLBn input before it is used in function PLB1 Function A 0x00 ...
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Table 32. PnSFDIMKA/PnSFDIMKB Registers Bit Map (Power-On Default 0x00) Bit Name R/W Description 7 Reserved N/A Cannot Be Used 6−0 IGN7−IGN1 R/W If high, mask the SFDn input before it is used in function PLB1 Function A ...
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ADM1060 Table 34. PnGPIIMK Registers Bit Map (Power-On Default 0x00) Bit Name R/W Description 7−4 AIMK4−AIMK1 R/W If high, mask the GPIn input before it is used in function A. 3−0 BIMK4−BIMK1 R/W If high, mask the GPIn input before ...
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PROGRAMMABLE DELAY BLOCK Each output of the PLBA is fed into a separate programmable delay block (PDB). The PDB enables the user to add a delay to the logic block output before it is applied to either a PDO or ...
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ADM1060 Table 37. Programmable Delay Block (PDB) Registers Default Hex Power-On Addr. Table Name Value 0C Table 38 P1PDBTIM 0x00 1C Table 38 P2PDBTIM 0x00 2C Table 38 P3PDBTIM 0x00 3C Table 38 P4PDBTIM 0x00 4C Table 38 P5PDBTIM 0x00 ...
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OUTPUTS PROGRAMMABLE DRIVER OUTPUTS The ADM1060 has nine programmable driver outputs (PDOs). These are the logic outputs of the device. Each PDO is normally controlled by a single PDB. Thus, the PDOs can be set up to assert when the ...
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ADM1060 Table 39. Programmable Driver Outputs Registers Hex Address Table Name 0D Table 40 P1PDOCFG 1D Table 40 P2PDOCFG 2D Table 40 P3PDOCFG 3D Table 40 P4PDOCFG 4D Table 40 P5PDOCFG 5D Table 40 P6PDOCFG 6D Table 40 P7PDOCFG 7D ...
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STATUS/FAULTS FAULT/STATUS REPORTING ON THE ADM1060 As discussed previously, any number of the PDOs can be programmed to assert under a set of preprogrammed conditions. These conditions could be a fault on an SFD, a change in status on a ...
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ADM1060 The functionality of the fault plane is best illustrated with an example. For instance, take VP1 to have an input supply of 5 UV/OV window set up on VP1. The ...
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Table 44. Bit Map for OVSTAT Register 0xD9 (Power-On Default 0x00) Bit Name R/W Description 7 Reserved N/A Cannot Be Used 6 VP4OV R If high, voltage on VP4 input is higher than the OV threshold. 5 VP3OV R If ...
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ADM1060 FAULT REGISTERS Table 49. List of Fault Registers Hex Addr. Table Name Default Power On Value DC Table 50 LATF1 0x00 DD Table 51 LATF2 0x00 Table 50. Bit Map for LATF1 Register 0xDC (Power-On Default 0x00) Bit Name ...
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MASK REGISTERS Table 52. List of Mask Registers Hex Addr. Table Name Default Power On Value 9D Table 53 ERRMASK1 0x00 9E Table 54 ERRMASK2 0x00 Table 53. Bit Map for ERRMASK1 Register 0x9D (Power-On Default 0x00) Bit Name R/W ...
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ADM1060 PROGRAMMING CONFIGURATION DOWNLOAD AT POWER-UP The configuration of the ADM1060—the UV/OV thresholds, glitch filter timeouts, PLB combinations, PDO pull-ups, etc.—is dictated by the contents of the RAM. The RAM is comprised of local latches that set the configuration. These ...
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Table 55. List of Configuration Update Registers Default Power- Hex Addr. Table Name On Value 90 Table 56 UPDCFG 0x00 Table 56. Bit Map for UPDCFG Register 0x90 (Power-On Default 0x00) Bit Name R/W Description 7–4 Reserved N/A Cannot be ...
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ADM1060 EEPROM The ADM1060 has 512 bytes of nonvolatile, electrically erasable programmable read-only memory (EEPROM) from register addresses 0xF800 to 0xF9FF. This may be used for permanent storage of data that will not be lost when the ADM1060 is pow- ...
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SCL SDA START BY MASTER FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED) SDA (CONTINUED) 1 SCL SDA START BY MASTER FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED) SDA ...
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ADM1060 WRITE OPERATIONS The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADM1060 are discussed below. The following abbreviations are used in the diagrams: S START P STOP R READ ...
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To set up a 2-byte EEPROM address for a subsequent read, write, block read, block write, or page erase. In this case, the command byte is the high byte of the EEPROM address from 0xF8 to 0xF9. The (only) ...
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ADM1060 BLOCK READ In this operation, the master device reads a block of data from a slave device. The start address for a block read must previously have been set. In the case of the ADM1060, this is done by ...
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PWRGD VIN VOUT LDO 0.9V_OUT 1 µ µ VCCP VDDCAP VP1 PDO1 15 VP2 10 PDO2 16 VP3 11 VP4 12 PDO3 17 PDO4 18 ADM1060 13 ...
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ADM1060 Table 57. ADM1060 Register Map BLOCK PLB1 0 P1PLBPOLA P1PLBIMKA P1SFDPOLA PLB2 1 P2PLBPOLA P2PLBIMKA P2SFDPOLA PLB3 2 P3PLBPOLA P3PLBIMKA P3SFDPOLA PLB4 3 P4PLBPOLA P4PLBIMKA P4SFDPOLA 4 P5PLBPOLA P5PLBIMKA P5SFDPOLA PLB5 PLB6 5 P6PLBPOLA P6PLBIMKA P6SFDPOLA ...
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PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS Table 58. Pin Function Descriptions Pin Mnemonic Function 1 A0 Logic Input. Controls the seventh bit (LSB) of the 7-bit Serial Bus Address Logic Input. Controls the sixth bit of the 7-bit Serial ...
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... ADM1060ARU–REEL7 –40°C to +85°C 1 EVAL–ADM1060EB 1 Contact factory for availability of the evaluation board. For general ADM1060 support, send email to: Figure 39. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters Package Description 28-lead TSSOP ...
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NOTES Rev Page ADM1060 ...
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ADM1060 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03470–0–12/03(B) Rev Page ...