EVAL-AD74111EBZ Analog Devices Inc, EVAL-AD74111EBZ Datasheet - Page 12

• Manufacturer Part Number: EVAL-AD74111EBZ
• Description: BOARD EVAL FOR AD74111
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD74111EBZ

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: AD74111
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

AD74111
there will be a fixed relationship between the instruction cycle
time of the DSP program and the AD74111, so a timer could be
used to accurately control the DAC updates. If a timer is not
available, the Multiframe-Sync (MFS) mode could be used to
generate a DFS pulse every 16 or 32 DCLKs, allowing the DSP
to accurately control the number of DCLKs between updates
using an autobuffering or DMA type technique. In all cases for
Slave mode operation, there should be 128 DCLKs (Normal
mode) or 256 DCLKs (Fast mode) between DAC updates. The
ADC operates in a similar manner; however, if the DSP does not
read an ADC result, this will appear only as a missed sample and
will not be audible. Slave mode is most suited to state-machine
type applications where the number of DCLKs and their
relationships to the other interface signals can be controlled.
(MM16)
DOUT
DIN
DFS
(MM16)
(MM16)
DOUT
DOUT
DFS
DFS
DIN
DIN
CONTROL
(16 BITS)
(16 BITS)
STATUS
CONTROL
(16 BITS)
(16 BITS)
(16 BITS)
(16 BITS)
(16 BITS)
(16 BITS)
STATUS
STATUS
STATUS
DAC
ADC
Figure 13. 16-Bit Mixed Mode, Word Length = 16 Bits
Figure 14. 16-Bit Mixed Mode, Word Length = 24 Bits
Figure 15. 16-Bit Data Mode, Word Length = 16 Bits
128 DCLKs (NORMAL MODE)
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
256 DCLKs (FAST MODE)
(16 BITS)
(16 BITS)
DAC
ADC
16 DCLKS
DAC DATA
ADC DATA
(24 BITS)
(24 BITS)
1/
1/
f
f
S
S
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
–12–
1/
f
S
CRD:3
DM/MM
0
0
1
1
0
0
1
1
CONTROL
(16 BITS)
(16 BITS)
(16 BITS)
(16 BITS)
(16 BITS)
STATUS
(16 BITS)
STATUS
STATUS
DAC
ADC
CRD:2 CRC:5, 4
DSP
Mode
0
1
0
1
0
1
0
1
(16 BITS)
(16 BITS)
Table II. Serial Mode Selection
DAC
ADC
Word
Width
16
16
16
16
>16
>16
>16
>16
Operating
Mode
16-Bit Data Mode
32-Bit Data Mode
16-Bit Mixed Mode 13
32-Bit Mixed Mode 17
16-Bit Data Mode
32-Bit Data Mode
16-Bit Mixed Mode 14
32-Bit Mixed Mode 18
CONTROL
(16 BITS)
(16 BITS)
STATUS
Figure
15
19
16
20
REV. 0