ATA6834-DK Atmel, ATA6834-DK Datasheet - Page 8

• Manufacturer Part Number: ATA6834-DK
• Description: BOARD BLDC MOTOR CTRL ATA6833/34
• Manufacturer: Atmel
• Type: MOSFET & Power Driverr

Specifications of ATA6834-DK

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6833 / ATA6834, ATmega32M1
• Primary Attributes: 3-Ph BLDC, IC with FET Driver, LIN Transceiver, Volt Regulator, Watchdog
• Secondary Attributes: LCD with Touch Screen on MCU Controller Board
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.4
Figure 3-4.
8
88% VCC
Reset and Watchdog Management
Atmel ATA6833/ATA6834 [Preliminary]
VCC
WD
/RESET
Timing Diagram of the Watchdog in Conjunction with the /RESET Signal
Reset and lead
time, no trigger
t
res
The watchdog timing is based on the trimmed internal watchdog oscillator. Its period time T
is determined by the external resistor R
function; a LOW signal disables it. Since WDD pin is equipped with an internal pull-up resistor
the watchdog is enabled by default. In order to keep the current consumption as low as possi-
ble the watchdog is switched off during Sleep Mode.
The timing diagram in
After power-up of the VCC regulator (VCC output exceeds 88% of its nominal value) /RESET
output stays LOW for the timeout period t
switches to HIGH. During the following time t
expected otherwise another external reset will be triggered.
When the watchdog has been correctly triggered for the first time, normal watch-dog operation
begins. A normal watchdog cycle consists of two time sections t
pulse for the time t
Rising edges on WD pin during t
is always the time of the last rising edge either on WD pin or on /RESET pin.
If the watchdog is disabled (WDD = LOW), only the initial reset for the time t
will be generated.
Additional resets will be generated if the VCC output voltage drops below 80% of its nominal
value.
The following example demonstrates how to calculate the timing scheme for valid watchdog
trigger pulses, which the external microcontroller has to provide in order to prevent undesired
resets.
t
d
trigger during lead time
Reset and lead time,
t
res
resshort
t
d
Figure 3-4
trigger edge
Watchdog
at /RESET if no valid trigger has been applied at pin WD during t
Watchdog cycle,
t
1
1
no trigger
shows the watchdog and external reset timing.
also cause a short pulse on /RESET. Start for such a cycle
WD
t
. A HIGH signal on WDD pin enables the watchdog
2
res
d
(typical 500ms) a rising edge at the input WD is
(typical 10ms). Subsequently /RESET output
t
Watchdog cycle, trigger
resshort
t
during t
1
2
1
window
and t
Watchdog trigger
t
2
in t
2
followed by a short
2
window
res
9122G–AUTO–10/10
after power-up
t
1
OSC
2
.