NBC124XXEVB ON Semiconductor, NBC124XXEVB Datasheet - Page 15

• Manufacturer Part Number: NBC124XXEVB
• Description: EVAL BOARD FOR NBC124XX
• Manufacturer: ON Semiconductor

Specifications of NBC124XXEVB

• Design Resources: NBC124XXEVB Gerber Files
• Main Purpose: Timing, PLL
• Embedded: No
• Utilized Ic / Part: NBC12429, NBC12430, NBC12439
• Primary Attributes: DIP Switch Controlled M & N Logic
• Secondary Attributes: Push Button or Externally Controlled P_Load
• Technology Type: Evaluation Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: NBC124XX
• Other names: NBC124XXEVBOS

dependent but the JEDEC specification is 1000 cycles. Both
Peak−to−Peak and RMS statistical values were measured.
over a long period of consecutive cycles compared to the
position of the perfect reference clock’s edge and is specified
by the number of cycles over which the jitter is measured.
The number of cycles used to look for the maximum jitter
varies by application but the JEDEC spec is 10,000 observed
cycles. Both Peak−to−Peak and RMS value statistical values
were measured.
Table 13. TYPICAL JITTER PERFORMANCE,
Cycle−to−Cycle (ps
Cycle−to−Cycle
(ps
Period (ps
Period Jitter is the edge placement deviation observed
RMS
)
JITTER
PP
Figure 11. Cycle−to−Cycle Jitter
)
T
0
T
JITTER(cycle−cycle)
PP
)
F
OUT
M Value
N Value
37.5
37.5
37.5
100
150
200
300
400
100
150
200
300
400
100
150
25
50
75
25
50
75
25
50
75
in MHz
= T
T
1
1
− T
0
200
98
11
1
200
105
13
66
2
3.3 V, 25°C with 16 MHz Crystal Input at Selected M and N Values
http://onsemi.com
200
91
13
79
4
15
200
106
106
17
8
jitter as a function of the output frequency for selected M and
N values using a 16 MHz crystal. Typical jitter values for
other M and N registers settings may be linearly
interpolated. The general trend is that as the VCO output
frequency is increased, primarily determined by the M
register setting, the output jitter will decrease. Alternate
combinations of M and N register values may produce the
same output frequency but with significantly different jitter
performance.
Table 13 shows the typical Period and Cycle−to−Cycle
300
58
1
6
300
59
39
2
9
300
55
42
4
9
300
67
10
56
8
400
43
1
6
400
52
2
8
400
51
32
4
8
400
44
35
8
7