NBC124XXEVB ON Semiconductor, NBC124XXEVB Datasheet - Page 12

• Manufacturer Part Number: NBC124XXEVB
• Description: EVAL BOARD FOR NBC124XX
• Manufacturer: ON Semiconductor

Specifications of NBC124XXEVB

• Design Resources: NBC124XXEVB Gerber Files
• Main Purpose: Timing, PLL
• Embedded: No
• Utilized Ic / Part: NBC12429, NBC12430, NBC12439
• Primary Attributes: DIP Switch Controlled M & N Logic
• Secondary Attributes: Push Button or Externally Controlled P_Load
• Technology Type: Evaluation Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: NBC124XX
• Other names: NBC124XXEVBOS

useful only for performance verification of the device itself.
However, the PLL bypass mode may be of interest at the
board level for functional debug. When T[2:0] is set to 110,
the device is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers.
The N divider drives the F
counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving
F
sent through the clock tree. Figure 7 shows the functional
setup of the PLL bypass mode. Because the S_CLOCK is a
CMOS level the input frequency is limited to 250 MHz or
less. This means the fastest the F
the S_CLOCK is 250 MHz as the minimum divide ratio of
the N counter is 1. Note that the M counter output on the
TEST output will not be a 50% duty cycle due to the way the
divider is implemented.
S_DATA
S_CLOCK
OUT
S_LOAD
Most of the signals available on the TEST output pin are
Ç Ç Ç Ç
Ç Ç Ç Ç
Ç Ç Ç Ç
Ç Ç Ç Ç
directly gives the user more control on the test clocks
SCLOCK
SDATA
S_CLOCK to S_LOAD
•
•
PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.
FREF_EXT
T2=T1=1, T0=0: Test Mode
SCLOCK is selected, MCNT is on TEST output, SCLOCK B N is on F
14−BIT
MCNT
SHIFT
REG
t
t
s
s
OUT
First
M COUNTER
T1
differential pair and the M
T0
T2
Bit
OUT
T2
PLL 12430
C1
SLOAD
pin can be toggled via
T1
Figure 7. Serial Test Clock Block Diagram
Figure 6. Serial Interface Timing Diagram
C2
t
t
h
h
T0
S_DATA to S_CLOCK
LATCH
C3
Reset
PLOAD
VCO_CLK
N1
C4
http://onsemi.com
N0
C5
DECODE
12
M8
C6
P_LOAD
T2
M[8:0]
N[1:0]
0
0
0
0
1
1
1
1
M7
C7
0
1
Figure 5. Parallel Interface Timing Diagram
M6
C8
T1
É É É É
É É É É
É É É É
0
0
1
1
0
0
1
1
MCNT
MCNT
FDIV4
FREF
HIGH
F
LOW
M5
OUT
C9
(1, 2, 4, 8)
OUT
N B
C10
M4
T0
0
1
0
1
0
1
0
1
pin.
7
0
TEST
MUX
t
s
M3
C11
SHIFT REGISTER OUT
HIGH
F
M COUNTER OUT
F
LOW
PLL BYPASS
F
(VIA ENABLE GATE)
REF
OUT
OUT
VALID
C12
M2
B 4
TEST (Pin 20)
F
TEST
C13
OUT
M1
É É É É
É É É É
É É É É
t
h
M, N to P_LOAD
Last
C14
Bit
M0