USB AUDIO 2.0 REFERENCE DESIGN XMOS, USB AUDIO 2.0 REFERENCE DESIGN Datasheet - Page 55

• Manufacturer Part Number: USB AUDIO 2.0 REFERENCE DESIGN
• Description: USB AUDIO 2.0 REFERENCE DESIGN
• Manufacturer: XMOS

Specifications of USB AUDIO 2.0 REFERENCE DESIGN

• Design Resources: USB AUDIO Schematic
• Main Purpose: Audio, Audio Processing
• Embedded: Yes
• Utilized Ic / Part: XS1-L1
• Primary Attributes: Audio data up to 24-bit @ 192kHz
• Secondary Attributes: I²S and S/PDIF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 880-1017

USB Audio Software Design Guide
void clockGen
void SpdifReceive
This function needs 1 thread and no memory other than ~2800 bytes of program
Clock generation and digital audio I/O handling.
Parameters
S/PDIF receiver.
code. It can do 11025, 12000, 22050, 24000, 44100, 48000, 88200, 96000,
and 192000 kHz.w
For a 100MHz reference clock, use a divider of 1 for 192000, 2 for
96000/88200, 4 for 48000/44100 on clock b. When the decoder encoun-
ters a long series of zeros it will lower the divider; when it encounters a short
series of 0-1 transitions it will increase the divider.
Output: whole word with bits 0-3 set to preamble.
Parameters
mitting samples
configuration functions.
clock
rupts
c_dig – channel connected to the
c_spdif_rx – channel connected to S/PDIF receive thread
c_adat_rx – channel connect to ADAT receive thread
p – port to output clock signal to drive external frequency synthesizer
c_audio – channel connected to the
p – S/PDIF output port
c – channel to output samples to
initial_divider – initial divide for initial estimate of sample rate
c_clk_int – channel connected to the
c_clk_ctl – channel connected to
c_config – An optional channel that will be passed on to the CODEC
( streaming chanend c_spdif_rx,
chanend c_adat_rx,
out port p,
chanend c_audio,
chanend c_clk_ctl,
chanend c_clk_int
( in buffered port:4 p,
streaming chanend c,
int initial_divider,
clock b
)
)
clockGen()
Endpoint0()
audio()
decouple()
thread
thread for receiving/trans-
for configuration of the
thread for clock inter-
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