DS50PCI402EVK/NOPB National Semiconductor, DS50PCI402EVK/NOPB Datasheet - Page 19

• Manufacturer Part Number: DS50PCI402EVK/NOPB
• Description: BOARD EVALUATION DS50PCI402
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS50PCI402EVK/NOPB

• Main Purpose: Interface, Transceiver, PCI Express
• Embedded: No
• Utilized Ic / Part: DS50PCI402
• Primary Attributes: 5 Gbps Quad Lane Bidirectional Buffer & Equalizer
• Secondary Attributes: 3.3V LVCMOS Input Tolerant for SMBus Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS50PC1402EVK/NOPB

IDLE AND RATE DETECTION TO EXTERNAL PINS
The functions of IDLE and RATE detection to external pins for
monitoring can be supported in SMBus mode. The external
GPIO pins of 19, 20, 46 and 47 will be changed and they will
serve as outputs for IDLE and RATE detect signals.
The following external pins should be set to auto detection:
RATE = F (FLOAT) – auto RATE detect enabled
TXIDLEA/B = F (FLOAT) – auto IDLE detect enabled
There are 4 GPIO pins that can be configured as outputs with
reg_4E[0].
To disable the external SMBus address pins, so pin 46 and
47 can be used as outputs:
Write 01'h to address 0x4E.
Care must be taken to ensure that only the desired status
block is enabled and attached to the external pin as the status
blocks can be OR’ed together internally. Register bits reg_47
[5:4] and bits reg_4C[7:6] are used to enable each of the sta-
tus block outputs to the external pins. The channel status
blocks can be internally OR’ed together to monitor more than
one channel at a time. This allows more information to be
presented on the status outputs and later if desired, a diag-
nosis of the channel identity can be made with additional
SMBus writes to register bits reg_47[5:4] and bits reg_4C
[7:6].
Below are examples to configure the device and bring the in-
ternal IDLE and RATE status to pins 19, 20, 46, 47.
19
To monitor the IDLE detect with two channels ORed (CH0
with CH2, CH1 with CH3, CH4 with CH6, CH5 with CH7):
Write 32'h to address 0x47.
The following IDLE status should be observable on the ex-
ternal pins:
pin 19 – CH0 with CH2,
pin 20 – CH1 with CH3,
pin 46 – CH4 with CH6,
pin 47 – CH5 with CH7.
Pin = HIGH (VDD) means IDLE is detected (no signal
present).
Pin = LOW (GND) means ACTIVE (data signal present).
To monitor the RATE detect with two channels ORed (CH0
with CH2, CH1 with CH3, CH4 with CH6, CH5 with CH7):
Write C0'h to address 0x4C.
The following RATE status should be observable on the ex-
ternal pins:
pin 19 – CH0 with CH2,
pin 20 – CH1 with CH3,
pin 46 – CH4 with CH6,
pin 47 – CH5 with CH7.
Pin = HIGH (VDD) means high data rate is detected (6 Gbps).
Pin = LOW (GND) means low rate is detected (3 Gbps).
www.national.com