DS50PCI402EVK/NOPB National Semiconductor, DS50PCI402EVK/NOPB Datasheet - Page 15

• Manufacturer Part Number: DS50PCI402EVK/NOPB
• Description: BOARD EVALUATION DS50PCI402
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS50PCI402EVK/NOPB

• Main Purpose: Interface, Transceiver, PCI Express
• Embedded: No
• Utilized Ic / Part: DS50PCI402
• Primary Attributes: 5 Gbps Quad Lane Bidirectional Buffer & Equalizer
• Secondary Attributes: 3.3V LVCMOS Input Tolerant for SMBus Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS50PC1402EVK/NOPB

SERIAL BUS INTERFACE DC SPECIFICATIONS
V
V
I
V
I
I
C
R
SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See
FSMB
TBUF
THD:STA
TSU:STA
TSU:STO
THD:DAT
TSU:DAT
T
T
T
T
t
t
t
PULLUP
LEAK-Bus
LEAK-Pin
F
R
POR
TIMEOUT
LOW
HIGH
LOW
IL
IH
DD
I
TERM
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Note 16: Recommended value. Parameter not tested in production.
Note 17: Recommended maximum capacitance load per bus segment is 400pF.
Note 18: Maximum termination voltage should be identical to the device supply voltage.
Note 19: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common
AC specifications for details.
Symbol
:SEXT
Data, Clock Input Low Voltage
Data, Clock Input High Voltage
Current Through Pull-Up Resistor
or Current Source
Nominal Bus Voltage
Input Leakage Per Bus Segment
Input Leakage Per Device Pin
Capacitance for SDA and SCL
External Termination Resistance
pull to V
10%
Bus Operating Frequency
Bus Free Time Between Stop and
Start Condition
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
Repeated Start Condition Setup
Time
Stop Condition Setup Time
Data Hold Time
Data Setup Time
Detect Clock Low Timeout
Clock Low Period
Clock High Period
Cumulative Clock Low Extend
Time (Slave Device)
Clock/Data Fall Time
Clock/Data Rise Time
Time in which a device must be
operational after power-on reset
DD
= 2.5V ± 5% OR 3.3V ±
Parameter
High Power Specification
(Note
(Note
Pullup V
(Note
Pullup V
(Note
(Note
At I
(Note
(Note
(Note
(Note
(Note
(Note
PULLUP
16)
16,
16,
16,
19)
19)
19)
19)
19)
19)
19)
DD
DD
, Max
Note
Note
Note
Figure 7
Conditions
= 3.3V,
= 2.5V,
15
17)
17,
17,
Note
Note
18)
18)
2.375
-200
Min
300
250
2.1
4.7
4.0
4.7
4.0
4.7
4.0
10
25
4
2000
1000
Typ
-15
+200
1000
Max
100
300
500
0.8
3.6
3.6
10
35
50
2
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Units
kHz
mA
ms
ms
ms
µA
µA
pF
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
Ω
Ω
V
V
V