SI5338-EVB Silicon Laboratories Inc, SI5338-EVB Datasheet - Page 16

• Manufacturer Part Number: SI5338-EVB
• Description: BOARD EVALUATION SI5338
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5338-EVB

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: Si5338
• Primary Attributes: 160 kHz to 700 MHz in LVPECL/LVDS,
• Secondary Attributes: USB Based GUI to Program, I2C/SMBus Compatible Interface, 1.8, 2.5, or 3.3 V
• For Use With/related Products: Si5330/34/38 Family
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1556

Si5338
3. Functional Description
3.1. Overview
The Si5338 is a high-performance, low-jitter clock
generator capable of synthesizing four independent
user-programmable clock frequencies up to 350 MHz
and select frequencies up to 710 MHz. The device
supports free-run operation using an external crystal, or
it can lock to an external clock for generating
synchronous clocks. The output drivers support four
differential clocks or eight single-ended clocks or a
combination of both. The output drivers are configurable
to support common signal formats, such as LVPECL,
LVDS, HCSL, CMOS, HSTL, and SSTL. Separate
output supply pins allow supply voltages of 3.3, 2.5, 1.8,
and 1.5 V to support the multi-format output driver. The
core voltage supply accepts 3.3, 2.5, or 1.8 V and is
independent from the output supplies.
Using its two-stage synthesis architecture and patented
high-resolution MultiSynth technology, the Si5338 can
generate four independent frequencies from a single
input frequency. In addition to clock generation, the
inputs can bypass the synthesis stage enabling the
Si5338 to be used as a high-performance clock buffer or
a combination of a buffer and generator.
For applications that need fine frequency adjustments,
such as clock margining, each of the synthesized
frequencies can be incremented or decremented in
user-defined steps as low as 1 ppm per step.
Output-to-output phase delays are also adjustable in
user-defined steps with an error of <20 ps to
compensate for PCB trace delays or for fine tuning of
setup and hold margins.
16
INTR
SDA
SCL
IN1
IN2
IN3
IN4
IN5
IN6
I2C_LSB/PDEC/FDEC
OEB/PINC/FINC
Osc
Control
Control & Memory
CLKIN
÷P1
FDBK
÷P2
(OTP)
NVM
Stage
Input
Figure 1. Si5338 Block Diagram
RAM
ref
fb
Frequency
Detector
Phase
Rev. 1.0
Synthesis
Stage 1
MultiSynth
(PLL)
VDD
A zero-delay mode is also available to help minimize
input-to-output delay. Spread spectrum is available on
each of the clock outputs for EMI-sensitive applications,
such as PCI Express.
Configuration and control of the Si5338 is mainly
handled through the I
features, such as output enable and frequency or phase
adjustments, can optionally be pin controlled. The
device has a maskable interrupt pin that can be
monitored for loss of lock or loss of input signal
conditions.
The device also provides the option of storing a user-
definable clock configuration in its non-volatile memory
(NVM), which becomes the default clock configuration
at power-up.
3.1.1. ClockBuilder™ Desktop Software
To simplify device configuration, Silicon Labs provides
ClockBuilder Desktop software, which can operate
stand alone or in conjunction with the Si5338 EVB.
When the software is connected to an Si5338 EVB it will
control both the supply voltages to the Si5338 as well as
the entire clock path within the Si5338. Clockbuilder
Desktop can also measure the current delivered by the
EVB regulators to each supply voltage of the Si5338. A
Si5338 configuration can be written to a text file to be
used by any system to configure the Si5338 via I
ClockBuilder
www.silabs.com/ClockBuilder
Windows Vista, and Windows 7.
÷N
Loop
Filter
VCO
Desktop
Synthesis
MultiSynth
MultiSynth
MultiSynth
MultiSynth
Stage 2
÷M3
÷M0
÷M1
÷M2
can
2
C/SMBus interface. Some
and runs on Windows XP,
be
Output
Stage
÷
÷
÷
÷
R3
R0
R1
R2
downloaded
VDDO0
CLK0A
CLK0B
VDDO1
CLK1A
CLK1B
VDDO2
CLK2A
CLK2B
VDDO3
CLK3A
CLK3B
2
C.
from