CDB5464U Cirrus Logic Inc, CDB5464U Datasheet - Page 28

• Manufacturer Part Number: CDB5464U
• Description: BOARD EVAL FOR CS5464 ADC
• Manufacturer: Cirrus Logic Inc
• Type: A/Dr

Specifications of CDB5464U

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5464
• Primary Attributes: Watt-Hour Meter
• Secondary Attributes: Graphical User Interface, SPI™ & USB Interfaces
• Product: Data Conversion Development Tools
• Maximum Clock Frequency: 4 MHz
• Interface Type: USB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• For Use With/related Products: CS5464
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1554; CDB-5464U

8. REGISTER DESCRIPTIONS
8.1 Page Register
8.1.1 Page
8.2 Page 0 Registers
8.2.1 Configuration (Config)
28
MSB
2
6
PC[7:0]
EWA
IMODE, IINV
iCPU
K[3:0]
Default = 0
Register Read and Write commands contain only 5 address bits. But the internal address bus of the CS5464 is
12 bits wide. Therefore, registers are organized into “Pages”. There are 128 pages of 32 registers each. The
Page register provides the 7 high-order address bits and selects one of the 128 register pages. Not all pages
are used,
Page is a write-only integer containing 7 bits.
Default = 1 (K=1)
EWA
PC7
23
15
7
-
1. “Default” = bit states after power-on or reset
2. DO NOT write a “1” to any unpublished register bit.
3. DO NOT write to any unpublished register address.
2
5
–
Address: 31, Write-only, can be written from ANY page.
2
4
PC6
22
14
and in the range of -1.0 ≤ value < 1.0 sample (OWR) intervals.
0 = Normal Outputs
10 = Low-going Pulse on New Interrupt
0 = Default
1 = Invert CPUCLK.
unsigned and in the range of 1 to 16. When zero, K = 16. At reset, K = 1.
Phase compensation for channel 1. Sets a delay in voltage, relative to current. Phase is signed
Allows the E1 and E2 pins to be configured as open-drain outputs.
1 = Open-drain Outputs
Interrupt configuration. Selects INT pin behavior.
00 = Low Logic Level When Asserted
01 = High Logic Level When Asserted
11 = High-going Pulse on New Interrupt
Inverts the CPUCLK output.
Clock divider. Divides MCLK by K to generate internal clock DCLK. (DCLK = MCLK/K). K is
6
-
-
2
3
2
–
2
PC5
Address: 0
21
13
5
-
-
2
1
LSB
2
0
IMODE
iCPU
PC4
20
12
4
PC3
IINV
K3
19
11
3
PC2
K2
18
10
2
-
PC1
K1
17
9
1
-
CS5464
DS682F1
PC0
K0
16
8
0
-