EVAL-ADF4252EBZ2 Analog Devices Inc, EVAL-ADF4252EBZ2 Datasheet - Page 11

• Manufacturer Part Number: EVAL-ADF4252EBZ2
• Description: BOARD EVAL ADF4252 NO VCO/FILTER
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF4252EBZ2

• Main Purpose: Timing, Frequency Synthesizer
• Embedded: No
• Utilized Ic / Part: ADF4252
• Primary Attributes: Dual Fractional-N PLL
• Secondary Attributes: Board excludes Loop Filter & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CIRCUIT DESCRIPTION
Reference Input Section
The reference input stage is shown in Figure 3. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
RF and IF Input Stage
The RF input stage is shown in Figure 4. The IF input stage is
the same. It is followed by a two-stage limiting amplifier to
generate the CML clock levels needed for the N counter.
RF INT Divider
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 255 are allowed.
INT, FRAC, MOD, and R Relationship
The INT, FRAC, and MOD values, in conjunction with the
RF R counter, make it possible to generate output frequencies
that are spaced by fractions of the RF phase frequency detector
(PFD). The equation for the RF VCO frequency (RF
where RF
oscillator (VCO).
REV. B
NC = NORMALLY CLOSED
NO = NORMALLY OPEN
RF
F
PFD
OUT
OUT
RF
RF
REF
=
IN
IN
=
REF
A
B
is the output frequency of external voltage controlled
IN
Figure 3. Reference Input Stage
F
PFD
NC
IN
GENERATOR
POWER-DOWN
Figure 4. RF Input Stage
SW1
CONTROL
×
×
BIAS



(
1
INT
NO
+
R
NC
D
SW3
SW2
)
+
2k
FRAC
MOD
100k
1.6V



2k
BUFFER
XOEB
A
V
GND
DD
1
REF
OUT
TO R
COUNTER
OUT
IN
) is
pin
(1)
(2)
–11–
REF
bit, R = the preset divide ratio of the binary 4-bit program-
mable reference counter (1 to 15), INT = the preset divide ratio of
the binary 8-bit counter (31 to 255), MOD = the preset modulus
ratio of binary 12-bit programmable FRAC counter (2 to 4095),
and FRAC = the preset fractional ratio of the binary 12-bit
programmable FRAC counter (0 to MOD).
RF R Counter
The 4-bit RF R counter allows the input reference frequency
(REF
the RF PFD. Division ratios from 1 to 15 are allowed.
IF R Counter
The 15-bit IF R counter allows the input reference frequency
(REF
the IF PFD. Division ratios from 1 to 32767 are allowed.
IF Prescaler (P/P + 1)
The dual modulus IF prescaler (P/P + 1), along with the IF A
and B counters, enables the large division ratio, N, to be realized
(N = PB + A). Operating at CML levels, it takes the clock from
the IF input stage and divides it down to a manageable frequency
for the CMOS IF A and B counters.
IF A and B Counters
The IF A and B CMOS counters combine with the dual modulus
IF prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are guaranteed to work when the
prescaler output is 150 MHz or less.
Pulse Swallow Function
The IF A and B counters, in conjunction with the dual modulus
IF prescaler, make it possible to generate output frequencies
that are spaced only by the reference frequency divided by R.
See Device Programming after Initial Power-Up section for
examples. The equation for the IF VCO (IF
where IF
oscillator (VCO), P = the preset modulus of IF dual modulus
prescaler, B = the preset divide ratio of the binary 12-bit counter
(3 to 4095), and A = the preset divide ratio of the binary 6-bit
swallow counter (0 to 63). F
INPUT STAGE
FROM RF
IN
IF
IN
IN
= the reference input frequency, D = RF REF
) to be divided down to produce the reference clock to
) to be divided down to produce the reference clock to
OUT
OUT
=
= the output frequency of the external voltage controlled
[
RF N DIVIDER
(
P
N-COUNTER
×
REG
B
INT
Figure 5. N Counter
)
+
A
]
×
PFD
F
PFD
is obtained using Equation 2.
MOD
REG
INTERPOLATOR
THIRD ORDER
FRACTIONAL
N = INT + FRAC/MOD
OUT
VALUE
ADF4252
FRAC
) frequency is
IN
doubler
TO PFD
(3)