AC164336 Microchip Technology, AC164336 Datasheet - Page 112

MODULE SOCKET FOR PM3 28/44QFN

AC164336

Manufacturer Part Number
AC164336
Description
MODULE SOCKET FOR PM3 28/44QFN
Manufacturer
Microchip Technology
Datasheet

Specifications of AC164336

Module/board Type
Socket Module - QFN
Product
Microcontroller Accessories
Lead Free Status / RoHS Status
Not applicable / Not applicable
For Use With/related Products
MPLAB® PM3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not applicable / Not applicable
dsPIC30F1010/202X
REGISTER 12-1:
DS70178C-page 110
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-4
bit 3-0
SYNCEN
R/W-0
R/W-0
PTEN
PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
Unimplemented: Read as ‘0’
PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
SESTAT: Special Event Interrupt Status bit
1 = Special Event Interrupt is pending
0 = Special Event Interrupt is not pending
SEIEN: Special Event Interrupt Enable bit
1 = Special Event Interrupt is enabled
0 = Special Event Interrupt is disabled
EIPU: Enable Immediate Period Updates bit
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
SYNCPOL: Synchronize Input Polarity bit
1 = SYNCIN polarity is inverted (low active)
0 = SYNCIN is high active
SYNCOEN: Primary Time Base Sync Enable bit
1 = SYNCO output is enabled
0 = SYNCO output is disabled
SYNCEN: External Time Base Synchronization Enable bit
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
SYNCSRC<2:0>: Sync Source Selection bits
000 = SYNCI
001 = Reserved
111 = Reserved
SEVTPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
1111 = 1:16 Postscale
.
.
| |
| |
R/W-0
U-0
PTCON: PWM TIME BASE CONTROL REGISTER
SYNCSRC<2:0>
W = Writable bit
‘1’ = Bit is set
PTSIDL
R/W-0
R/W-0
SESTAT
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SEIEN
R/W-0
R/W-0
R/W-0
R/W-0
EIPU
SEVTPS<3:0>
© 2006 Microchip Technology Inc.
x = Bit is unknown
SYNCPOL
R/W-0
R/W-0
SYNCOEN
R/W-0
R/W-0
bit 8
bit 0

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