COP8-EMFA-68N National Semiconductor, COP8-EMFA-68N Datasheet - Page 48

• Manufacturer Part Number: COP8-EMFA-68N
• Description: EMULATOR NULL TARGET
• Manufacturer: National Semiconductor

Specifications of COP8-EMFA-68N

• Accessory Type: Emulator Null Target
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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11.0 MICROWIRE/PLUS
13.0 Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
0000 to 006F
0070 to 007F
xx80 to xx8F
xx90 to xx9F
xxA0
xxA1
xxA2
xxA3
xxA4
xxA5
xxA6
xxA7
xxA8
xxA9
xxAA
xxAB
xxAC
xxAD
xxAE
xxAF
xxB0 to xxBF
xxC0
xxC1
xxC2
xxC3
S/ADD REG
Address
FIGURE 30. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High
On-Chip RAM bytes (112 bytes)
Unused RAM Address Space (Reads As
All Ones)
Unused RAM Address Space (Reads
Undefined Data)
Reserved
Port A Data Register
Port A Configuration Register
Port A Input Pins (Read Only)
Reserved for Port A
Port B Data Register
Port B Configuration Register
Port B Input Pins (Read Only)
Reserved for Port B
ISP Address Register Low Byte
(ISPADLO)
ISP Address Register High Byte
(ISPADHI)
ISP Read Data Register (ISPRD)
ISP Write Data Register (ISPWR)
Reserved
Reserved
Reserved
High Speed Timers Control Register
(HSTCR)
Reserved
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA Lower
Byte
Timer T2 Autoload Register T2RA Upper
Byte
Contents
(Continued)
48
xxC4
xxC5
xxC6
xxC7
xxC8
xxC9
xxCA
xxCB
xxCC
xxCD
xxCE
xxCF
xxD0
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
xxD7 to xxDB
xxDC
xxDD
xxDE
xxDF
xxE0
xxE1
xxE2
xxE3 to xxE5
S/ADD REG
Address
Timer T2 Autoload Register T2RB Lower
Byte
Timer T2 Autoload Register T2RB Upper
Byte
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
MIWU Edge Select Register
(Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
A/D Converter Control Register (ENAD)
A/D Converter Result Register High Byte
(ADRSTH)
A/D Converter Result Register Low Byte
(ADRSTL)
Reserved
Idle Timer Control Register (ITMR)
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Reserved
Port H Data Register
Port H Configuration Register
Port H Input Pins (Read Only)
Reserved for Port H
Reserved
Flash Memory Write Timing Register
(PGMTIM)
ISP Key Register (ISPKEY)
Reserved
Contents
20026439