COP8-EMFA-68N National Semiconductor, COP8-EMFA-68N Datasheet - Page 38

• Manufacturer Part Number: COP8-EMFA-68N
• Description: EMULATOR NULL TARGET
• Manufacturer: National Semiconductor

Specifications of COP8-EMFA-68N

• Accessory Type: Emulator Null Target
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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9.0 Interrupts
9.1 INTRODUCTION
The device supports nine vectored interrupts. Interrupt
sources include Timer 1, Timer 2, Timer T0, Port L Wake-up,
Software Trap, MICROWIRE/PLUS, and External Input.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.
9.2 MASKABLE INTERRUPTS
All interrupts other than the Software Trap are maskable.
Each maskable interrupt has an associated enable bit and
pending flag bit. The pending bit is set to 1 when the interrupt
condition occurs. The state of the interrupt enable bit, com-
bined with the GIE bit determines whether an active pending
flag actually triggers an interrupt. All of the maskable inter-
rupt pending and enable bits are contained in mapped con-
trol registers, and thus can be controlled by the software.
A maskable interrupt condition triggers an interrupt under the
following conditions:
1. The enable bit associated with that interrupt is set.
2. The GIE bit is set.
3. The device is not processing a non-maskable interrupt.
An interrupt is triggered only when all of these conditions are
met at the beginning of an instruction. If different maskable
(If a non-maskable interrupt is being serviced, a
maskable interrupt must wait until that service routine is
completed.)
FIGURE 23. Interrupt Block Diagram
38
The Software trap has the highest priority while the default
VIS has the lowest priority.
Each of the 8 maskable inputs has a fixed arbitration ranking
and vector.
Figure 23 shows the Interrupt block diagram.
interrupts meet these conditions simultaneously, the highest-
priority interrupt will be serviced first, and the other pending
interrupts must wait.
Upon Reset, all pending bits, individual enable bits, and the
GIE bit are reset to zero. Thus, a maskable interrupt condi-
tion cannot trigger an interrupt until the program enables it by
setting both the GIE bit and the individual enable bit. When
enabling an interrupt, the user should consider whether or
not a previously activated (set) pending bit should be ac-
knowledged. If, at the time an interrupt is enabled, any
previous occurrences of the interrupt should be ignored, the
associated pending bit must be reset to zero prior to en-
abling the interrupt. Otherwise, the interrupt may be simply
enabled; if the pending bit is already set, it will immediately
trigger an interrupt. A maskable interrupt is active if its asso-
ciated enable and pending bits are set.
An interrupt is an asychronous event which may occur be-
fore, during, or after an instruction cycle. Any interrupt which
occurs during the execution of an instruction is not acknowl-
edged until the start of the next normally executed instruc-
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