DM-COP8/20D National Semiconductor, DM-COP8/20D Datasheet - Page 42

• Manufacturer Part Number: DM-COP8/20D
• Description: CABLE FOR DEBUG MODULE 20-DIP
• Manufacturer: National Semiconductor

Specifications of DM-COP8/20D

• Accessory Type: 20-DIP Target Cable
• For Use With/related Products: MetaLink Debug Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DM-COP8/20D

2.4
The COPSAx7 family is based on a modified Harvard architecture, which allows data
tables to be accessed directly from program memory. This is very important with modern
microcontroller-based applications, since program memory is usually ROM or EPROM,
while data memory is usually RAM. Consequently data tables usually need to be
contained in ROM or EPROM, so they are not lost when the microcontroller is powered
down. In a modified Harvard architecture, instruction fetch and memory data transfers
can be overlapped with a two stage pipeline, which allows the next instruction to be
fetched from program memory while the current instruction is being executed using data
memory. This is not possible with a Von Neumann single-address bus architecture.
The COPSAx7 family supports a software stack scheme that allows the user to
incorporate many subroutine calls. This capability is important when using High Level
Languages. With a hardware stack, the user is limited to a small fixed number of stack
levels.
2.5
Real estate and board configuration considerations demand maximum space and pin
efficiency, particularly given today's high integration and small product form factors.
Microcontroller users try to avoid using large packages to get the I/O needed. Large
packages take valuable board space and increases device cost, two trade-offs that
microcontroller designs can ill afford.
The COP8 family offers a wide range of packages and do not waste pins: up to 90.9% (or
40 pins in the 44 -pin package) are devoted to useful I/O.
2-4
INTERRUPT
ARCHITECTURE
PACKAGING/PIN EFFICIENCY
COP8SAx7 MICROCONTROLLER
WAKEUP
DECODE
ILLEGAL
DETECT
CLOCK
RESET
LOGIC
INSTR
COND
HALT
IDLE
CPU REGISTERS
ICNTRL
CNTRL
PSW
SP
A
B
X
MODIFIED HARVARD
Figure 2-1 COP8SAx7 Block Diagram
ARCHITECTURE
TIMER
16 BIT
C 8 BIT CORE
T1
ALU
MICRO
WIRE/
PLUS
ADDR
REG
PC
TIMER
IDLE
4k/2k/1k
EPROM
BYTES
T0
OTP
BYTES
128/64
RAM
WATCH
DOG
WAKEUP
INPUT
MULTI
D
I/O PORTS
F
C
G
L