HW-FLYLEADS Xilinx Inc, HW-FLYLEADS Datasheet - Page 18

• Manufacturer Part Number: HW-FLYLEADS
• Description: LEAD WIRES FLYING CABLE III/IV
• Manufacturer: Xilinx Inc

Specifications of HW-FLYLEADS

• Accessory Type: Parallel Cable
• For Use With/related Products: Xilinx FPGA, CPLDS, Platform Flash PROMs, XC18V00 PROMs, System ACE MPM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1473

Table 8: AC Operating Characteristics
X-Ref Target - Figure 30
DS300 (v3.2) May 14, 2008
Product Specification
Symbol
on negative edge of TCK_CCLK_SCK
TMS_PROG_SS and TDI_DIN_MOSI
T
T
T
T
T
CPD
TSU
CSU
TPD
CLK
Platform Cable USB asserts
Notes:
1. All times are in nanoseconds and are relative to the target system interface connector.
2. T
3. T
4. Propagation delays associated with buffers on the target system must be taken into account to satisfy the minimum setup times.
TDO_DONE_MISO
R
TCK_CCLK_SCK
TMS_PROG_SS/
Clock Period
Cable Propagation Delay Time
TDI_DIN_MOSI (TMS_PROG_SS)
relative to the negative edge
of TCK_CCLK_SCK @ 24 MHz
Target Setup Time
TDI_DIN_MOSI (TMS_PROG_SS)
relative to the positive edge
of TCK_CCLK_SCK @ 24 MHz
Cable Setup Time
TDO_DONE_MISO relative to the
positive edge
of TCK_CCLK_SCK @ 24 MHz
Target Propagation Delay Time
TDO_DONE_MISO relative to the
negative edge
of TCK_CCLK_SCK @ 24 MHz
TDI_DIN_MOSI
TSU
CSU
Min is the minimum setup time guaranteed by Platform Cable USB relative to the positive edge of TCK_CCLK_SCK.
Min is the minimum setup required by Platform Cable USB to properly sample TDO_DONE_MISO.
Description
Figure 30: Platform Cable USB Timing Diagram
T
CLK
T
CPD
T
TSU
TCK_CCLK_SCK_S
CK frequency:
Target system V
Target system V
Target system V
Target system V
www.xilinx.com
Target device samples TMS_PROG_SS and
TDI_DIN_MOSI on positive edge of TCK_CCLK_SCK
Conditions
REF
REF
REF
REF
:
:
:
:
T
TPD
Target device asserts TDO_DONE_MISO
on negative edge of TCK_CCLK_SCK
750 kHz
24 MHz
3.3V
2.5V
1.8V
3.3V
2.5V
1.8V
3.3V
2.5V
1.8V
3.3V
2.5V
1.8V
Platform cable USB samples
TDO_DONE_MISO approxi-
T
mately 15 ns after positive
edge of TCK_CCLK_SCK
CSU
41.66
TBD
TBD
TBD
TBD
Min
11
11
Platform Cable USB
1333
Max
TBD
TBD
TBD
TBD
9.2
10
DS300_28_021707
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
18