591-2304-013F Dialight, 591-2304-013F Datasheet - Page 7
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591-2304-013F
Manufacturer Part Number
591-2304-013F
Description
LED GREEN PRISM/CBI 570NM SMD
Manufacturer
Dialight
Series
Prism®, CBI®r
Specifications of 591-2304-013F
Color
Green
Voltage Rating
1.8V
Current
20mA
Lens Style/size
Round, 2.84mm
Configuration
Single
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lens Type
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Other names
350-2316-2
Functional Overview
The CY7C21701KV18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface, which operates with a read
latency of two and half cycles when DOFF pin is tied HIGH.
When DOFF pin is set LOW or connected to V
behaves in DDR I mode with a read latency of one clock cycle.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input and output timing is referenced
from the rising edge of the input clocks (K and K).
All synchronous data inputs (D
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q
controlled by the rising edge of the input clocks (K and K).
All synchronous control (R/W, LD, BWS
input registers controlled by the rising edge of the input clock (K).
CY7C21701KV18 is described in the following sections.
Read Operations
The CY7C21701KV18 is organized internally as two arrays of
512K x 36. Accesses are completed in a burst of 2 sequential
36-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to the address inputs is stored
in the read address register. Following the next two K clock rise,
the corresponding 36-bit word of data from this address location
is driven onto the Q
On the subsequent rising edge of K, the next 36-bit data word is
driven onto the Q
the rising edge of the input clock (K and K). To maintain the
internal logic, each read access must be allowed to complete.
Read accesses can be initiated on every rising edge of the
positive input clock (K).
When read access is deselected, the CY7C21701KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the output following the next
rising edge of the negative input clock (K). This enables for a
transition between devices without the insertion of wait states in
a depth expanded memory.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register. On the following K clock rise, the data
presented to D
data register, provided BWS
subsequent rising edge of the negative input clock (K) the infor-
mation presented to D
register, provided BWS
data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of
the positive input clock (K). Doing so pipelines the data flow such
that 36 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
When the write access is deselected, the device ignores all
inputs after the pending write operations are completed.
Document Number: 001-57344 Rev. *A
[35:0]
[35:0]
[35:0]
is latched and stored into the 36-bit write
. The requested data is valid 0.45 ns from
[35:0]
[3:0]
using K as the output timing reference.
are asserted active. The 72 bits of
is also stored into the write data
[x:0]
[3:0]
[x:0]
) pass through output registers
) pass through input registers
are asserted active. On the
[X:0]
) inputs pass through
SS
the device
Byte Write Operations
Byte write operations are supported by the CY7C21701KV18. A
write operation is initiated as described in the
section. The bytes that are written are determined by BWS
BWS
36-bit data words. Asserting the appropriate Byte Write Select
input during the data portion of a write latches the data being
presented and writes it into the device. Deasserting the Byte
Write Select input during the data portion of a write enables the
data stored in the device for that byte to remain unaltered. This
feature can be used to simplify read, modify, or write operations
to a byte write operation.
DDR Operation
The CY7C21701KV18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C21701KV18 requires two No
Operation (NOP) cycle during transition from a read to a write
cycle. At higher frequencies, some applications require third
NOP cycle to avoid contention.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information is stored because
the SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the read(s),
the stored data from the earlier write is written into the SRAM
array. This is called a Posted write.
If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the DDR II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free-running clocks and are
synchronized to the input clock of the DDR II+. The timing for the
echo clocks is shown in the
21.
1
, BWS
2
, and BWS
SS
to allow the SRAM to adjust its output
3
, which are sampled with each set of
Switching Characteristics
CY7C21701KV18
,
with V
Write Operations
DDQ
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= 1.5V. The
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