HFBR-5963LZ Avago Technologies US Inc., HFBR-5963LZ Datasheet - Page 2

• Manufacturer Part Number: HFBR-5963LZ
• Description: TXRX MMF FE ATM SONET OC-3 2X5
• Manufacturer: Avago Technologies US Inc.

Specifications of HFBR-5963LZ

• Applications: Ethernet
• Data Rate: 155MBd
• Wavelength: 1300nm
• Voltage - Supply: 2.97 V ~ 3.63 V
• Connector Type: LC Duplex
• Mounting Type: Through Hole
• Supply Voltage: 3.3V
• Wavelength Typ: 1300nm
• Leaded Process Compatible: Yes
• Optical Fiber Type: TX/RX
• Optical Rise Time: 3/2.2ns
• Optical Fall Time: 3/2.2ns
• Jitter: 0.4/0.3ns
• Operating Temperature Classification: Commercial
• Peak Wavelength: 1308/1380nm
• Package Type: DIP With Connector
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.63V
• Output Current: 50mA
• Operating Temp Range: 0C to 70C
• Mounting: Snap Fit To Panel
• Pin Count: 10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Receiver Section
The receiver section of the HFBR-5963xxZ utilizes an
InGaAs PIN photodiode coupled to a custom silicon tran-
simpedance preamplifier IC. It is packaged in the optical
subassembly portion of the receiver.
This PIN/preamplifier combination is coupled to a custom
quantizer IC which provides the final pulse shaping for
the logic output and the signal detect function. The data
output is differential. The data output is PECL compat-
ible, ECL referenced (shifted) to a +3.3 V power supply.
The receiver outputs, data output and data out bar, are
squelched at signal detect deassert. The signal detect
output is single ended. The signal detect circuit works by
sensing the level of the received signal and comparing
this level to a reference. The SD output is +3.3 V TTL.
Package
The overall package concept for the Avago transceiver
consists of three basic elements; the two optical subas-
semblies, an electrical subassembly, and the housing as
illustrated in the block diagram in Figure 1.
The package outline drawing and pin out are shown in
Figures 2 and 5. The details of this package outline and
pin out are compliant with the multisource definition of
the 2 x 5 DIP. The low profile of the Avago transceiver
design complies with the maximum height allowed for
the LC connector over the entire length of the package.
Figure 1. Block Diagram
2
DATA IN
DATA IN
DATA OUT
DATA OUT
SIGNAL
DETECT
LED DRIVER IC
QUANTIZER IC
R
T
X
X
SUPPLY
SUPPLY
R
T
X
X
GROUND
GROUND
The optical subassemblies utilize a high-volume assembly
process together with low-cost lens elements which result
in a cost- effective building block.
The electrical subassembly consists of a high volume mul-
tilayer printed circuit board on which the ICs and various
surface-mounted passive circuit elements are attached.
The receiver section includes an internal shield for the elec-
trical and optical subassemblies to ensure high immunity
to external EMI fields.
The outer housing including the LC ports is molded of filled
nonconductive plastic to provide mechanical strength.
The solder posts of the Avago design are isolated from the
internal circuit of the transceiver.
The transceiver is attached to a printed circuit board
with the ten signal pins and the two solder posts which
exit the bottom of the housing. The two solder posts
provide the primary mechanical strength to withstand the
loads imposed on the transceiver by mating with the LC
connector fiber cables.
PIN PHOTODIODE
PRE-AMPLIFIER
SUBASSEMBLY
LED
OPTICAL
SUBASSEMBLY
LC
RECEPTACLE