MT36HTS51272FY-667A3D3 Micron Technology Inc, MT36HTS51272FY-667A3D3 Datasheet - Page 21

• Manufacturer Part Number: MT36HTS51272FY-667A3D3
• Description: MODULE DDR2 4GB 240FBDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36HTS51272FY-667A3D3

• Memory Type: DDR2 SDRAM
• Memory Size: 4GB
• Speed: 667MT/s
• Package / Case: 240-FBDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240FBDIMM
• Device Core Size: 72b
• Organization: 512Mx72
• Total Density: 4GByte
• Chip Density: 1Gb
• Package Type: FBDIMM
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Number Of Elements: 36
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Assumptions for All Parameters
Table 9:
PDF: 09005aef822148b0/source: 09005aef82214898
HTS36C512x72F_2.fm - Rev. A 4/06 EN
Parameter/Condition
Idle current, single or last FBDIMM: L0 state, idle (0 BW); primary channel
enabled, secondary channel disabled, CKE HIGH; command and address lines
stable, DDR2 SDRAM clock active.
Idle current, first FBDIMM: L0 state, idle (0 BW); primary and secondary
channels enabled, CKE HIGH; command and address lines stable, DDR2 SDRAM
clock active.
Idle current, DDR2 SDRAM power-down: L0 state, idle (0 BW); primary and
secondary channels enabled, CKE HIGH; command and address lines floated, DDR2
SDRAM clock active; ODT and CKE driven LOW.
Active Power: L0 state; 50% DDR2 SDRAM BW, 67% READ, 33% WRITE; primary
and secondary channels enabled, CKE HIGH; DDR2 SDRAM clock active.
Active Power, data pass-through: L0 state; 50% DDR2 SDRAM BW to
downstream FBDIMM, 67% READ, 33% WRITE; primary and secondary channels
enabled; command and address lines stable, CKE HIGH; DDR2 SDRAM clock active.
Channel standby: Average power over 42 frames where the channel enters and
exits L0s; DDR2 SDRAM devices Idle (0 BW); CKE LOW; command and address lines
floated; DDR2 SDRAM lock active, ODE and CKE driven LOW.
Training: Primary and secondary channels enabled; 100% toggle on all channel
lanes; DDR2 SDRAM devices idle (0 BW); CKE HIGH, command and address lines
stable; DDR2 SDRAM clock active.
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Specifications and Conditions
DDR2 I
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Specifications and Conditions – 4GB
• primary channel drive strength at 100 percent with de-emphasis at –6.5dB, secondary
• Address and data fields are pseudo-random, which provides a 50 percent toggle rate
• Assuming 1 ACTIVATE command and 1 READ/WRITE command per BL = 4 transfer,
• Ten southbound lanes and 14 northbound lanes are enabled and active.
SPD-specific assumptions:
• Number of devices on the specific FBDIMM assumed
• Termination of command, address, and control is actual value used on the FBDIMM
• ECC as per the specific FBDIMM
• SPD specifies ΔT
AMB power-specification assumptions:
• Specific ECC FBDIMM assumed (72-bit data, 14 lanes northbound with DDR2
• Modeled with 27Ω termination for command, address, and clocks, and 47Ω termina-
• AMB specification specifies current for each rail
channel drive strength at 60 percent with de-emphasis at –3dB when enabled.
on DDR2 SDRAM data lines and link lanes when data is being transferred.
BL = 4.
SDRAMs as defined in configuration options of this data sheet)
tion for control
240-Pin 4GB DDR2 SDRAM FBDIMM (DR, FB, x72)
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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Specifications and Conditions
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Symbol
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ACTIVE
ACTIVE
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TRAINING
IDLE
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IDLE
_L0
_0
_1
_2
S
_1
_2
©2006 Micron Technology, Inc. All rights reserved.
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Preliminary
Units
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