MT9VDDT6472PHG-335F2 Micron Technology Inc, MT9VDDT6472PHG-335F2 Datasheet - Page 16
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MT9VDDT6472PHG-335F2
Manufacturer Part Number
MT9VDDT6472PHG-335F2
Description
MODULE DDR SDRAM 512MB 200SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT9VDDT1672PHG-335D2.pdf
(33 pages)
Specifications of MT9VDDT6472PHG-335F2
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
512Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.4A
Number Of Elements
9
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT9VDDT6472PHG-335F2
Manufacturer:
MICRON
Quantity:
1 001
Table 15: I
DDR SDRAM components only;
Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
t
once per clock cyle; Address and control inputs changing once
every two clock cycles
OPERATING CURRENT: One device bank; Active-Read-Precharge;
Burst = 4
and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
=
changing once per clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge;
(MIN); DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle; CK =
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle;
changing twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four bank interleaving READs (BL=4) with
auto precharge with,
and control inputs change only during Active READ, or WRITE
commands
RC (MIN);
t
CK MIN; CKE = HIGH; Address and other control inputs
;
t
RC =
t
CK =
t
t
RC (MIN);
CK =
DD
t
CK (MIN); DQ, DM and DQS inputs changing
Specifications and Conditions – 1GB
t
CK (MIN); I
t
t
CK (MIN); DQ, DM, and DQS inputs
RC =
t
CK =
t
t
CK =
RC (MIN);
0.2V
t
t
RC = RAS (MAX);
t
IN
OUT
CK =
CK (MIN); I
t
CK (MIN); CKE = LOW
= V
= 0mA
t
REF
CK (MIN); CKE = (LOW)
t
CK =
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
for DQ, DQS, and DM
OUT
t
t
t
REFC =
REFC = 7.8125µs
CK (MIN); Address
= 0mA; Address
t
CK =
t
RFC (MIN)
t
CK
t
RC =
t
16
CK
T
A
+70°C; V
SYMBOL
I
I
I
I
I
I
I
DD 4 W
I
I
DD 3 N
DD 4 R
I
DD 5 A
I
I
DD 2 P
DD 2 F
DD 3 P
DD 0
DD 1
DD 5
DD 6
DD 7
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
= V
1,040
1,280
1,320
1,240
2,320
3,240
-335
360
280
360
40
80
40
DD
Q = +2.5V ±0.2V
MAX
1,040
1,280
1,320
1,240
2,320
3,200
-262
360
280
360
40
80
40
©2004 Micron Technology, Inc. All rights reserved.
-26A/
1,160
1,440
1,600
1,680
2,640
3,880
-265
480
240
360
80
80
72
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ADVANCE
21, 28,
21, 28,
20, 41
20, 41
20, 41
20, 43
24, 43
20, 42
43
44
43
20
9