MT9VDDT6472Y-265D2 Micron Technology Inc, MT9VDDT6472Y-265D2 Datasheet - Page 11
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MT9VDDT6472Y-265D2
Manufacturer Part Number
MT9VDDT6472Y-265D2
Description
MODULE SDRAM DDR 512MB 184DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT9VDDT6472Y-265D2.pdf
(16 pages)
Specifications of MT9VDDT6472Y-265D2
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
266MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
512Mb
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.305A
Number Of Elements
9
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT9VDDT6472Y-265D2
Manufacturer:
ITT
Quantity:
6 965
Table 12:
PDF: 09005aef80e119b2/Source: 09005aef80e11976
DD9C16_32_64x72.fm - Rev. D 1/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock
cycle; V
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle;
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank
interleaving reads (BL = 4) with auto precharge;
t
READ or WRITE commands
CK =
RC =
CK =
t
t
t
t
t
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
CK (MIN); Address and control inputs change only during active
CK =
CK =
IN
t
RC =
= V
t
t
REF
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
t
t
t
RAS (MAX);
I
Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
CK =
CK =
DD
for DQ, DM, and DQS
t
CK =
Specifications and Conditions – 512MB
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
t
CK (MIN); I
OUT
t
CK =
= 0mA
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
t
CK (MIN); DQ, DM, and DQS inputs
OUT
= 0mA; Address and control inputs
t
RC =
t
RC =
t
t
REFC =
REFC = 7.8125µs
t
RC (MIN);
t
t
RC (MIN);
CK =
11
t
RFC (MIN)
t
CK (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1,170
1,440
1,485
1,395
2,610
3,600
-262
Electrical Specifications
405
315
450
45
90
45
©2003 Micron Technology, Inc. All rights reserved
-26A/
1,035
1,305
1,305
1,215
2,520
3,150
-265
360
270
405
45
90
45
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA