MT9VDDT6472AY-335D1 Micron Technology Inc, MT9VDDT6472AY-335D1 Datasheet - Page 12

• Manufacturer Part Number: MT9VDDT6472AY-335D1
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDT6472AY-335D1

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.575A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Presence-Detect
Table 13:
Table 14:
Serial Presence-Detect Data
PDF: 09005aef808f912d/Source: 09005aef808f8ccd
DD9C16_32_64x72A.fm - Rev. E 11/07 EN
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current: SCL = SDA = V
Power supply current: SCL clock frequency = 100 kHz
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
Clock/data fall time
Clock/data rise time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
Serial Presence-Detect EEPROM AC Operating Conditions
Notes:
OUT
IN
= 3mA
OUT
= GND to V
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.
128MB, 256MB, 512MB (x72, ECC, SR): 184-Pin DDR SDRAM UDIMM
= GND to V
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
DD
- 0.3V; All other inputs = V
DD
DD
12
SS
or V
t
DD
WRC) is the time from a valid stop condition of a write
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
t
HIGH
Symbol
LOW
f
WRC
t
t
BUF
V
SCL
AA
DH
t
t
t
R
F
DDSPD
I
V
V
V
I
I
I
I
LO
CC
SB
OL
LI
IH
IL
V
DDSPD
Min
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
–
–
–
–
–
Min
–1.0
2.3
Serial Presence-Detect
–
–
–
–
–
× 0.7
©2003 Micron Technology, Inc. All rights reserved.
Max
300
300
400
0.9
50
10
–
–
–
–
–
–
–
–
–
V
V
DDSPD
DDSPD
Max
3.6
0.4
2.0
10
10
30
Units
kHz
ms
µs
µs
ns
ns
ns
µs
µs
µs
ns
µs
ns
µs
µs
+ 0.5
× 0.3
Notes
Units
mA
µA
µA
µA
1
2
2
3
4
V
V
V
V