MT9VDDT3272PHG-265G2 Micron Technology Inc, MT9VDDT3272PHG-265G2 Datasheet - Page 22
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MT9VDDT3272PHG-265G2
Manufacturer Part Number
MT9VDDT3272PHG-265G2
Description
MODULE SDRAM DDR 256MB 200SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT9VDDT1672PHG-335D2.pdf
(33 pages)
Specifications of MT9VDDT3272PHG-265G2
Memory Type
DDR SDRAM
Memory Size
256MB
Speed
266MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
72b
Organization
32Mx72
Total Density
256MByte
Chip Density
256Mb
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.35A
Number Of Elements
9
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
41. Random addressing changing and 50 percent of
42. Random addressing changing and 100 percent of
43. CKE must be active (high) during the entire time a
44. I
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. I
similar to I
address and control inputs to remain stable.
REF later.
DD
2N specifies the DQ, DQS, and DM to be
DD
2F except I
DD
2Q specifies the
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
DD
2Q is
22
45. Whenever the operating frequency is altered, not
46. Leakage number reflects the worst case leakage
47. When an input signal is HIGH or LOW, it is
48. The -335 speed grade will operate with
200-PIN DDR SDRAM SODIMM
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
= 40ns and
frequency.
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2F is “worst case.”
DD
t
RAS (MAX) = 120,000ns at any slower
2F, I
DD
2N, and I
©2004 Micron Technology, Inc. All rights reserved.
DD
2Q are similar,
ADVANCE
t
RAS (MIN)