MT4LSDT864HG-133G2 Micron Technology Inc, MT4LSDT864HG-133G2 Datasheet - Page 8

• Manufacturer Part Number: MT4LSDT864HG-133G2
• Description: MODULE SDRAM 64MB 144SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4LSDT864HG-133G2

• Memory Type: SDRAM
• Memory Size: 64MB
• Speed: 133MHz
• Package / Case: 144-SODIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 144SODIMM
• Device Core Size: 64b
• Organization: 8Mx64
• Total Density: 64MByte
• Chip Density: 128Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 600mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use. For 32MB and 64MB, M12 (A12) is undefined, but
should be driven LOW during loading of the mode reg-
ister.
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
ented, with the burst length being programmable, as
shown in Figure 4, Mode Register Definition Diagram.
The burst length determines the maximum number of
column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 1, 2, 4, or
8 locations are available for both the sequential and
the interleaved burst types, and a full-page burst is
available for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in the Table 6,
Burst Definition Table, on page 9.
uniquely selected by A1–Ai (where i is the most signifi-
cant column address bit for a given device configura-
tion) when the burst length is set to two; by A2–Ai
when the burst length is set to four; and by A3–Ai when
the burst length is set to eight. See Note 8 of Table 6,
Burst Definition Table, on page 9 for Ai values. The
remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. Full-
page bursts wrap within the page if the boundary is
reached, as shown in Table 6, Burst Definition Table,
on page 9.
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
Mode register bits M0–M2 specify the burst length,
The mode register must be loaded when all device
Read and write accesses to the SDRAM are burst ori-
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
The block is
8
32MB and 64MB Module
128MB Module
M12, M11, M10 = “0, 0, 0”
to ensure compatibility
with future devices.
to ensure compatibility
*Should program
Figure 4: Mode Register Definition
with future devices.
M11, M10 = “0, 0”
*Should program
32MB, 64MB, 128MB (x64, SR)
Reserved*
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Reserved* WB
12
11
A11
A12
Reserved*
10
A10
11
A11
144-PIN SDRAM SODIMM
9
10
A9
A10
Op Mode
WB
M9
0
1
8
9
A8
A9
Op Mode
7
8
A7
A8
CAS Latency
7
6
Diagram
A7
A6
Programmed Burst Length
M8
0
Single Location Access
-
CAS Latency
6
5
Write Burst Mode
A6
A5
5
M7
4
A5
0
-
A4
BT
©2004 Micron Technology, Inc. All rights reserved.
4
A4
3
A3
M3
BT
Defined
M6-M0
0
1
3
Burst Length
A3
2
-
M6
M2
A2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
Burst Length
2
A2
M1
M5
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
1
A1
M0
M4
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
A1
0
A0
0
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
Mode Register (Mx)
Interleaved
Burst Type
Sequential
1
2
4
8
Address Bus
Mode Register (Mx)
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8