MT36VDDF25672Y-335D2 Micron Technology Inc, MT36VDDF25672Y-335D2 Datasheet - Page 24

• Manufacturer Part Number: MT36VDDF25672Y-335D2
• Description: MODULE SDRAM DDR 2GB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36VDDF25672Y-335D2

• Memory Type: DDR SDRAM
• Memory Size: 2GB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 256Mx72
• Total Density: 2GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 3.24A
• Number Of Elements: 36
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

pdf: 09005aef80772fd2, source: 09005aef8075ebf6
DDF36C128_256x72G.fm - Rev. D 9/04 EN
40. The current Micron part operates below the slow-
41. For -335, -262, -26A, and -265, I
42. Random address changing and 50 percent of data
43. Random address changing and 100 percent of
44. CKE must be active (high) during the entire time a
45. I
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
to be 35mA per DDR SDRAM device at 100 MHz.
changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. I
similar to I
REF later.
DD
2N specifies the DQ, DQS, and DM to be
DD
2F except I
DD
2Q specifies the
DD
3N is specified
DD
2Q is
24
46. Whenever the operating frequency is altered, not
47. Leakage number reflects the worst case leakage
48. When an input signal is HIGH or LOW, it is
49. The -335 speed grade will operate with
address and control inputs to remain stable.
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
= 40ns and
frequency.
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2F is “worst case.”
1GB, 2GB (x72, ECC, DR)
DD
t
RAS (MAX) = 120,000ns at any slower
2F, I
184-PIN DDR RDIMM
DD
2N, and I
©2004 Micron Technology, Inc. All rights reserved.
DD
2Q are similar,
t
RAS (MIN)