MT36VDDF25672Y-335D2 Micron Technology Inc, MT36VDDF25672Y-335D2 Datasheet - Page 19

• Manufacturer Part Number: MT36VDDF25672Y-335D2
• Description: MODULE SDRAM DDR 2GB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36VDDF25672Y-335D2

• Memory Type: DDR SDRAM
• Memory Size: 2GB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 256Mx72
• Total Density: 2GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 3.24A
• Number Of Elements: 36
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC
Notes: 1–5, 14; notes appear following parameter tables; 0°C
Table 18: DDR SDRAM Component Electrical Characteristics and Recommended AC
Notes: 1–5, 14; notes appear following parameter tables; 0°C
pdf: 09005aef80772fd2, source: 09005aef8075ebf6
DDF36C128_256x72G.fm - Rev. D 9/04 EN
AC CHARACTERISTICS
PARAMETER
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to V
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Operating Conditions (-335 and -262 Speed Grades) (Continued)
Operating Conditions (-26A, -265, and -202 Speed Grades)
DD
CL = 2.5
CL = 2
19
SYMBOL
SYMBOL
t
t
t
t
WPRES
t
CK (2.5)
t
t
t
t
t
DQSCK
t
t
t
t
WPRE
t
t
t
WPST
t
t
t
XSNR
XSRD
CK (2)
DQSQ
T
RPRE
T
DQSH
RPST
t
REFC
DIPW
DQSL
DQSS
t
WTR
RRD
REFI
VTD
t
NA
t
WR
t
t
t
DSH
t
t
t
A
t
DSS
A
t
AC
CH
DH
IH
DS
HP
HZ
CL
LZ
F
+70°C; V
+70°C; V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7.5/10
MIN
0.25
-0.75
-0.75
-0.75
200
MIN
t
0.9
0.4
0.4
0.45
0.45
1.75
0.35
0.35
0.75
0.90
12
15
75
QH -
7.5
0.5
0.5
0.2
0.2
0
1
0
-26A/-265
DD
DD
t
-335
CH,
t
= V
1GB, 2GB (x72, ECC, DR)
= V
DQSQ
MAX
t
70.3
+0.75
+0.75
+0.75
MAX
1.1
0.6
0.6
7.8
CL
0.55
0.55
1.25
DD
DD
0.5
13
13
Q = +2.5V ±0.2V
Q = +2.5V ±0.2V
184-PIN DDR RDIMM
MIN
0.25
200
MIN
0.9
0.4
0.4
0.45
0.45
0.35
0.35
0.75
t
-0.8
15
15
75
-0.8
-0.8
0.6
0.6
0.2
0.2
1.1
1
QH -
0
10
0
8
2
t
CH,
-262
-202
©2004 Micron Technology, Inc. All rights reserved.
t
DQSQ
MAX
MAX
t
+0.8
0.55
0.55
+0.8
1.25
+0.8
70.3
CL
0.6
1.1
0.6
0.6
7.8
13
13
UNITS NOTES
UNITS NOTES
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
CK
ns
CK
ns
CK
ns
CK
ns
µs
µs
ns
ns
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
18, 19
40, 47
23, 27
23, 27
22, 23
16, 37
16, 37
40,47
22
21
38
38
17
21
26
26
27
30
12