MT36LSDF12872G-13ED1 Micron Technology Inc, MT36LSDF12872G-13ED1 Datasheet
MT36LSDF12872G-13ED1
Specifications of MT36LSDF12872G-13ED1
Related parts for MT36LSDF12872G-13ED1
MT36LSDF12872G-13ED1 Summary of contents
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... Row Addressing Column Addressing Module Ranks PDF: 09005aef80b1835d/Source: 09005aef80b18348 SD36C128_256x72G.fm - Rev. E 6/05 EN Products and specifications discussed herein are subject to change by Micron without notice. 1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM www.micron.com/products/modules Figure 1: Standard Low-Profile Options • Package 168-pin DIMM (standard) 168-pin DIMM (lead-free) • ...
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Table 3: Part Numbers Part Number MT36LSDT12872G-13E__ MT36LSDT12872Y-13E__ MT36LSDT12872G-133__ MT36LSDT12872Y-133__ MT36LSDT25672G-13E__ MT36LSDT25672Y-13E__ MT36LSDT25672G-133__ MT36LSDT25672Y-133__ Note: The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes. Example: MT36LSDT12872G-133B1. PDF: ...
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Pin Assignments and Descriptions Table 4: Pin Assignment 168-Pin DIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol CB1 DQ0 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbol order; refer to Table 4 on page 3 for more information Pin Numbers 27, 111, 115 RAS#, CAS#, WE# 42, 79, 125, 163 128 30, 45, 114, 129 28, ...
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... All resistor values are 10Ω unless otherwise specified. ‘t’ indicates top portion of stacked SDRAM. ‘b’ indicates bottom portion of stacked SDRAM. Per industry standard, Micron modules utilize various component speed grades, as ref- erenced in the module part number guide at ing.html. Standard modules use the following SDRAM devices: MT48LC64M4A2TG (1GB); ...
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Figure 3: Functional Block Diagram RS0# RS1# RDQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RDQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CB0 CB1 CB2 CB3 RS2# RS3# RDQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 ...
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... LOW) where the input signals pass through the register/buffer to the SDRAM devices on the same clock. A phase-lock loop (PLL) on the modules is used to redrive the clock to the SDRAM devices to minimize system clock loading. (CK0 is connected to the PLL, and CK1, CK2, and CK3 are terminated ...
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Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational pro- cedures other than those specified may result in undefined operation. Once power is applied to V defined as a signal cycling within timing constraints specified for ...
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Figure 4: Mode Register Definition Diagram M12, M11, M10 = “0, 0,0” to ensure compatibility with future devices. PDF: 09005aef80b1835d/Source: 09005aef80b18348 SD36C128_256x72G.fm - Rev. E 6/05 EN 1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM A12 ...
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Table 6: Burst Definition Table Burst Length Full Page Notes: 1. For full-page accesses 2,048 (1GB); y= 4,096 (2GB). 2. For will select the block of two burst; A0 selects the starting column within ...
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Figure 5: CAS Latency Diagram COMMAND COMMAND Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of ...
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Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combi- nations of values for M7 and M8 are reserved for future use and/or test modes. The pro- grammed burst length applies to ...
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Commands Table 8 provides a quick reference of available commands. This is followed by a written description of each command. For a more detailed description of commands and opera- tions refer to the 256Mb or 512Mb SDRAM component data sheets. ...
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Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections ...
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Table 10: I Specifications and Conditions – 1GB DD SDRAM components only; Notes 11, 13; notes appear on page 19; V Parameter/Condition Operating current: Active mode; Burst = 2; READ or WRITE ...
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Capacitance Table 12: Capacitance Note: 2; notes appear on page 19 Parameter Input capacitance: Address and command Input capacitance: CKE Input capacitance: CK Input capacitance: S#, DQMB Input/Output capacitance: DQ PDF: 09005aef80b1835d/Source: 09005aef80b18348 SD36C128_256x72G.fm - Rev. E 6/05 EN 1GB, ...
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AC Operating Specifications Table 13: SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes 11, 31; notes appear on page 19 AC Characteristic Parameter Access time from CLK (pos. edge) Address hold time Address setup ...
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Table 14: AC Functional Characteristics Notes 11, 31; notes appear on page 19 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup ...
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Notes 1. All voltages referenced This parameter is sampled. V test biased at 1.4V with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are ...
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... V (MAX for a pulse width ≤ 3ns, and the pulse width cannot be greater than one t WR, and PRECHARGE commands). CKE may 7.5ns; for -13E and t RAS used in -13E speed grade modules is calculated from 45ns. 20 undershoot overshoot for pin A12 is limited RP) begins 7ns for -13E; ...
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Timing Requirements and Switching Characteristics Table 15: Register Timing Requirements and Switching Characteristics Register Symbol f clock t Propagation delay, single rank pd1 SSTL t propagation delay, dual rank pd2 bit pattern by JESD82 ...
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... The system used for experimental purposes is a dual-processor 600 MHz work station, fully loaded with four MT36LSDT12872G modules. Case temperatures charted represent worst-case component locations on modules installed in the internal slots of the system. 3. Temperature versus air speed data is obtained by performing experiments with the system motherboard removed from its case and mounted in a Eiffel-type low air speed wind tun- nel ...
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Serial Presence Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 8, and ...
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Figure 9: Definition of Start and Stop SCL SDA Figure 10: Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Table 17: EEPROM Device Select Code The most significant bit (b7) is sent first ...
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Figure 11: SPD EEPROM Timing Diagram SCL t SU:STA SDA IN SDA OUT Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic ...
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Table 20: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to V Parameter/Condition Stop condition setup time WRITE cycle time Notes avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling ...
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Table 21: Serial Presence-Detect Matrix “1”/”0”: Serial data, “driven to HIGH”/”driven to LOW”; V Byte Description 0 Number of bytes used by Micron 1 Total number of SPD memory bytes 2 Memory type 3 Number of row addresses 4 Number ...
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Table 21: Serial Presence-Detect Matrix (Continued) “1”/”0”: Serial data, “driven to HIGH”/”driven to LOW”; V Byte Description 35 Data signal input hold time, 36–40 Reserved 41 Device minimum active/auto-refresh time, 42–61 Reserved 62 SPD revision 63 Checksum for bytes 0–62 ...
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Module Dimensions Figure 12: 168-Pin DIMM Dimensions – Standard PCB U1 U2 0.079 (2.00) R (2X) 0.118 (3.00) (2X) 0.118 (3.00) TYP. 0.250 (6.35) TYP. 0.118 (3.00) PIN 1 TYP. U15 U16 PIN 168 Note:All dimensions in inches (millimeters); PDF: ...
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Figure 13: 168-Pin DIMM Dimensions – Low-Profile 0.079 (2.00) R (2X 0.118 (3.00) (2X) 0.118 (3.00) 0.250 (6.35) PIN 1 0.118 (3.00) U15 U16 U17 PIN 168 Note:All dimensions in inches (millimeters); 8000 S. Federal Way, P.O. ...