MT18VDDF6472DG-40BG2 Micron Technology Inc, MT18VDDF6472DG-40BG2 Datasheet - Page 13
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MT18VDDF6472DG-40BG2
Manufacturer Part Number
MT18VDDF6472DG-40BG2
Description
MODULE SDRAM DDR 512MB 184DIMM
Manufacturer
Micron Technology Inc
Specifications of MT18VDDF6472DG-40BG2
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
400MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
256Mb
Access Time (max)
500ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.836A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Commands
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
Table 8:
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NOTE:
Table 9:
Used to mask write data; provided coincident with the corresponding data
pdf: 09005aef8074e85b, source: 09005aef8072fe49
DDF18C64_128x72G.fm - Rev. C 11/04 EN
NAME (FUNCTION)
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
WRITE Enable
WRITE Inhibit
1. DESELECT and NOP are functionally interchangeable.
2. BA0
3. BA0
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
5. A10 LOW: BA0
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0
Table 8, Commands Truth Table, and Table 9, DM
HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
bursts with auto precharge enabled and for WRITE bursts.
BA1 are “Don’t Care.”
= 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0
to be written to the selected mode register.
–
–
–
BA1 provide device bank address and A0
BA1 provide device bank address; A0
BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
Commands Truth Table
DM Operation Truth Table
–
BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0
–
A9, A11 (512MB) or A0–A9, A11, A12 (1GB) provide column address; A10
–
A12 provide row address.
13
CS#
H
L
L
L
L
L
L
L
L
of commands and operations, refer to the 256Mb or
512Mb DDR SDRAM component data sheet.
RAS#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
X
H
H
H
H
L
L
L
L
512MB, 1GB (x72, ECC, SR)
CAS#
H
H
X
H
H
L
L
L
L
WE#
H
H
H
H
X
L
L
L
L
Bank/Row
©2004 Micron Technology, Inc. All rights reserved.
Bank/Col
Bank/Col
Op-Code
ADDR
–
Code
A12 provide the op-code
X
X
X
X
DM
H
L
NOTES
6, 7
1
1
2
3
3
4
5
8
Valid
DQS
X
–