MT16VDDF12864HG-335F2 Micron Technology Inc, MT16VDDF12864HG-335F2 Datasheet
MT16VDDF12864HG-335F2
Specifications of MT16VDDF12864HG-335F2
Related parts for MT16VDDF12864HG-335F2
MT16VDDF12864HG-335F2 Summary of contents
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... PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 512MB, 1GB (x64, DR) 200-PIN DDR SODIMM MT16VDDF6464H – 512MB MT16VDDF12864H – 1GB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 200-Pin SODIMM (MO-224) 512MB Module 1.50in. (38.10mm) 1GB Module 1.50in. (38.10mm) OPTIONS • ...
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... MT16VDDF6464HG-265__ MT16VDDF6464HY-265__ MT16VDDF12864HG-335__ MT16VDDF12864HY-335__ MT16VDDF12864HG-262__ MT16VDDF12864HY-262__ MT16VDDF12864HG-26A__ MT16VDDF12864HY-26A__ MT16VDDF12864HG-265__ MT16VDDF12864HY-265__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current Revision codes. Example: MT16VDDF6464HG-265A1. pdf: 09005aef80a77a90, source: 09005aef80a646bc DDF16C64_128x64HG.fm - Rev. D 9/04 EN CONFIGURATION ...
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Table 3: Pin Assignment (200-Pin SODIMM Front) PIN PIN PIN SYMBOL SYMBOL 101 REF DQ19 103 SS 5 DQ0 55 DQ24 105 7 DQ1 57 V 107 DQ25 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS 118, 119, 120 CAS#,RAS# 35, 37, 158, 160 CK0, CK0# CK1, CK1# 95, 96 CKE0, CKE1 ...
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... No Connect: These pins should be left unconnected. DNU — Do Not Use: These pins are not connected on this module, but are assigned pins on other modules in this product family. 5 512MB, 1GB (x64, DR) 200-PIN DDR SODIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... DD V U17 REF SDA SA1 SA2 Standard modules use the following DDR SDRAM devices: MT46V32M8FN (512MB); MT46V64M8FN (1GB) Lead-free modules use the following DDR SDRAM devices: MT46V32M8BN (512MB); MT46V64M8BN (1GB) www.micron.com/ 6 512MB, 1GB (x64, DR) 200-PIN DDR SODIMM DM CS# DQS DM CS# DQS ...
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... REF V SS Standard modules use the following DDR SDRAM devices: MT46V32M8FN (512MB); MT46V64M8FN (1GB) Lead-free modules use the following DDR SDRAM devices: www.micron.com/ MT46V32M8BN (512MB); MT46V64M8BN (1GB) Micron Technology, Inc., reserves the right to change products or specifications without notice. 7 512MB, 1GB (x64, DR) ...
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... General Description The MT16VDDF6464H and MT16VDDF12864H are high-speed CMOS, dynamic random-access, 512MB and 1GB memory modules organized in a x64 configu- ration. DDR SDRAM modules use internally config- ured quad-bank DDR DRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double ...
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Burst Length Read and write accesses to DDR SDRAM devices are burst oriented, with the burst length being program- mable, as shown in Figure 5, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evalua- tion. (When the device exits ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 512MB DD Notes: 1–5, 8, 10, 12, 47; DDR SDRAM devices only; notes appear on pages 18–21; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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Table 13: I Specifications and Conditions – 1GB DD Notes: 1–5, 8, 10, 12, 47; DDR SDRAM devices only; notes appear on pages 18–21; 0°C T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); CK ...
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Table 14: Capacitance Note: 11; notes appear notes appear on pages 18–21 PARAMETER Input/Output Capacitance: DQ, DQS,DM Input Capacitance: Command and Address, RAS#, CAS#, WE# Input Capacitance:CK, CK#, CKE, S# Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC ...
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Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 12–15, 29, 48; notes appear on pages 18–21; 0°C AC CHARACTERISTICS PARAMETER DQ-DQS hold, DQS to first non-valid, per access Data hold ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 QHS). The data valid window ...
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Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9V, which- ever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either - ...
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CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t REF later. 44. ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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... NOTE: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across all modules. 2. The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 13, Data Validity, and Figure ...
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Table 16: EEPROM Device Select Code Most significant bit (b7) is sent first. SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 17: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read Sequential ...
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Table 18: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 20: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 28 BYTE DESCRIPTION 0 Number of Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 ...
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... Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met The value of RP, RCD, and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef80a77a90, source: 09005aef80a646bc DDF16C64_128x64HG.fm - Rev. D 9/04 EN ENTRY (VERSION) 0.8ns (-335 1ns (-262/-26A/-265) 0 ...
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Figure 17: 200-PIN SODIMM Dimensions – 512MB 0.079 (2.00 (2X) 0.071 (1.80) (2X) U7 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (.99) TYP PIN 1 U9 U15 PIN 200 NOTE: All dimensions are in inches (millimeters); pdf: 09005aef80a77a90, ...
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Figure 18: 200-PIN SODIMM Dimensions – 1GB 0.079 (2.00) R (2X) U1 0.071 (1.80) (2X) U5 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (.99) TYP PIN 1 U9 U13 PIN 200 NOTE: All dimensions are in inches (millimeters); Data Sheet ...