MT9VDDF6472Y-40BF3 Micron Technology Inc, MT9VDDF6472Y-40BF3 Datasheet
MT9VDDF6472Y-40BF3
Specifications of MT9VDDF6472Y-40BF3
Related parts for MT9VDDF6472Y-40BF3
MT9VDDF6472Y-40BF3 Summary of contents
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... ECC, SR) PC3200 184-PIN DDR SDRAM RDIMM MT9VDDF3272 – 256MB MT9VDDF6472 – 512MB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 184-Pin DIMM (MO-206) Low-Profile 1.125in. (28.58mm) Very Low-Profile 0.72in. (18.29mm) OPTIONS • Package 184-pin DIMM (standard) 184-pin DIMM (lead-free) • ...
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... DENSITY MT9VDDF3272G-40B__ 256MB 256MB MT9VDDF3272Y-40B__ 512MB MT9VDDF6472G-40B__ MT9VDDF6472Y-40B__ 512MB NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9VDDF3272G-40BB1. pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23 DDAF9C32_64x72G.fm - Rev. C 9/04 EN 256MB, 512MB (x72, ECC, SR) PC3200 ...
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Table 3: Pin Assignment (184-Pin DIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL DQ17 47 REF 2 DQ0 25 DQS2 DQ1 DQS0 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL 10 RESET# 63, 65, 154 WE#, CAS#, RAS# 137, 138 CK0, CK0# 21 157 52, ...
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... Supply Ground. SS Supply Serial EEPROM positive power supply: +2.3V to +3.6V. DDSPD DNU — Do Not Use: Thes pins are not connected on these modules, but are assigned pins on other modules in this product family. NC — No Connect: These pins should be left unconnected. 5 184-PIN DDR SDRAM RDIMM DESCRIPTION Micron Technology, Inc ...
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... T RCKE0: DDR SDRAMs E RWE#: DDR SDRAMs R S RESET# Standard modules use the following DDR SDRAM devices: MT46V32M8FG (256MB); MT46V64M8FG (512MB) Lead-free modules use the following DDR SDRAM devices: www.micron.com/ MT46V43M8BG (256MB); MT46V64M8BG (512MB) 6 184-PIN DDR SDRAM RDIMM DM CS# DQS DQ DQ32 DQ DQ33 ...
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... RCAS#: DDR SDRAMs V RCKE0: DDR SDRAMs RWE#: DDR SDRAMs RESET Standard modules use the following DDR SDRAM devices: MT46V32M8FG (256MB); MT46V64M8FG (512MB) Lead-free modules use the following DDR SDRAM devices: www.micron.com/ MT46V43M8BG (256MB); MT46V64M8BG (512MB) 7 184-PIN DDR SDRAM RDIMM DM CS# DQS DQ ...
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... DDR SDRAM modules uss internally con- figured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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Vio- lating either of these requirements will result in unspecified operation. Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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TER SET command with bits A7 and A9–A12 each set to zero, bit A8 set to one, and bits A0–A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- Voltage on V ...
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Table 12: IDD Specifications and Conditions – 256MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 18–20; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); DQ, DM and ...
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Table 13: IDD Specifications and Conditions – 512MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 18–20; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); DQ, DM and ...
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Table 14: Capacitance Note: 11; notes appear on pages 18–20 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: ...
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Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 8, 10, 12; notes appear on pages 18–20; 0°C AC CHARACTERISTICS PARAMETER PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 QHS). The data valid ...
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Figure 8: Pull-Down Characteristics 160 140 120 100 0.0 0.5 1 (V) (V) OUT OUT 39. During initialization DDQ equal to or less than V + 0.3V. Alternatively ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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Table 16: Register Timing Requirements and Switching Characteristics Note: 1 REGISTER SYMBOL PARAMERTER f Clock Frequency clock t Clock to Output Time pd t Reset to Output Time PHL SSTL t Pulse Duration w (bit pattern by JESD82-3 t Differential ...
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Table 17: PLL Clock Driver Timing Requirements and Switching Characteristics Note: 1 PARAMETER SYMBOL Operating Clock Frequency Input Duty Cycle Stabilization Time Cycle to Cycle Jitter Static Phase Offset Output Clock Skew Period Jitter Half-Period Jitter t Input Clock Slew ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Fig- ure 11, Data Validity, and Figure 12, Definition ...
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Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 19: EEPROM Operating Modes MODE Current Address Read Random Address Read Sequential Read ...
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Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Output Low Voltage 3mA ...
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Table 22: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 Number of Row Addresses ...
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Table 22: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 46 Reserved 47 DIMM Height 48–61 Reserved 62 SPD Revision 63 Checksum For Bytes 0-62 64 Manufacturer’s JEDEC ID Code 65-71 Manufacturer’s JEDEC ID Code ...
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... U2 U3 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) TYP. 0.091 (2.30) 2.55 (64.77) TYP. PIN 184 Figure 16: 184-PIN DIMM DDR Modules – Very Low-Profile 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) TYP. 0.091 (2.30) 2 ...
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Data Sheet Designation Released (No Mark): This data sheet contains mini- mum and maximum limits specified over the complete power supply and temperature range for production 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, ...