MT8VDDT6464HDG-335F2 Micron Technology Inc, MT8VDDT6464HDG-335F2 Datasheet - Page 17
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MT8VDDT6464HDG-335F2
Manufacturer Part Number
MT8VDDT6464HDG-335F2
Description
MODULE DDR 512MB 200-SODIMM
Manufacturer
Micron Technology Inc
Specifications of MT8VDDT6464HDG-335F2
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
64Mx64
Total Density
512MByte
Chip Density
512Mb
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
800mA
Number Of Elements
8
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Notes
pdf: 09005aef80b575ca, source: 09005aef806e1d28
DDA8C32_64x64HDG.fm - Rev. D 9/04 EN
10. I
11. This parameter is sampled. V
1. All voltages referenced to V
2. Tests for AC timing, I
3. Outputs measured with equivalent load:
4. AC timing and I
5. The AC and DC input level specifications are as
6. V
7. V
8. I
9. Enables on-chip refresh and address counters.
characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.
swing of up to 1.5V in the test environment, but
input timing is still referenced to V
crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V
and V
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V
DC value. Thus, from V
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V
system supply for signal termination resistors, is
expected to be set equal to V
variations in the DC level of V
rates. Specified values are obtained with mini-
mum cycle time at CL = 3 for -40B with the out-
puts open.
properly initialized, and is averaged at the defined
cycle rate.
V
25°C, V
DD
DD
REF
TT
DD
Q = +2.5V ±0.2V, V
is not applied directly to the device. V
is dependent on output loading and cycle
specifications are tested after the device is
is expected to equal V
IH
OUT
(AC).
REF
(DC) = V
REF
Output
(V
by-pass capacitor.
OUT
may not exceed ±2 percent of the
)
DD
DD
V
DD
tests may use a V
TT
REF
50
Q/2, V
30pF
, and electrical AC and DC
Reference
Point
Ω
DD
= V
SS
DD
Q/2, V
.
SS
OUT
REF
Q/2 of the transmit-
REF
, f = 100 MHz, T
DD
.
(peak to peak) =
and must track
= +2.5V ±0.2V,
REF
REF
is allowed
(or to the
IL
IL
-to-V
TT
(ACV)
is a
A
IH
=
17
256MB, 512MB (x64, DR) PC3200
12. For slew rates less than 1 V/ns and greater than or
13. The CK/CK# input reference level (for timing ref-
14. Inputs are not recognized as valid until V
15. The output timing reference level, as measured at the
16.
17. The intent of the Don’t Care state after completion
18. This is not a device limit. The device will operate
19. It is recommended that DQS be valid (HIGH or
20. MIN (
21. The refresh period 64ms. This equates to an aver-
0.2V. DM input is grouped with I/O pins, reflecting
the fact that they are matched in loading.
equal to 0.5 V/ns. If slew rate is less than 0.5 V/ns,
timing must be derated:
per each 100 mV/ns reduction in slew rate from
500 mV/ns, while
exceeds 4.5 V/ns, functionality is uncertain. For -
40B, slew rates must be ≥ 0.5 V/ns.
erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V
lizes. Exception: during the period before V
stabilizes, CKE ≤ 0.3 x V
timing reference point indicated in Note 3, is V
t
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
of the postamble is the DQS-driven signal should
either be high, low, or high-Z and that any signal
transition within the input switching region must
follow valid input requirements. If DQS transi-
tions to HIGH above V
not transition to LOW below V
to
with a negative value, but system performance
could be degraded due to bus turnaround.
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on
smallest multiple of
absolute value for the respective parameter.
(MAX) for I
ple of
value for
age refresh rate of 7.8125µs. However, an AUTO
REFRESH command must be asserted at least
once every 70.3µs; burst refreshing or posting by
HZ and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSH (MIN).
t
RC or
t
CK that meets the maximum absolute
t
t
LZ transitions occur in the same access
RAS.
DD
200-PIN DDR SODIMM
t
t
RFC) for I
measurements is the largest multi-
DQSS.
t
IH is unaffected. If slew rate
t
CK that meets the minimum
REF
DD
IH
t
DD
IS has an additional 50ps
Q is recognized as LOW.
(DC) MIN, then it must
.
measurements is the
IH
©2004 Micron Technology, Inc.
(DC) MIN prior
REF
TT
stabi-
t
.
RAS
REF