MT8VDDT6464HDG-335F2 Micron Technology Inc, MT8VDDT6464HDG-335F2 Datasheet - Page 11

• Manufacturer Part Number: MT8VDDT6464HDG-335F2
• Description: MODULE DDR 512MB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6464HDG-335F2

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 800mA
• Number Of Elements: 8
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Commands
Operation Truth Table, below, provide a general refer-
ence of available commands. For a more detailed
Table 8:
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NOTE:
Table 9:
Used to mask write data; provided coincident with the corresponding data
pdf: 09005aef80b575ca, source: 09005aef806e1d28
DDA8C32_64x64HDG.fm - Rev. D 9/04 EN
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A12 provide row address.
3. BA0–BA1 provide device bank address; A0–A8 (256MB) or A0–A9 (512MB) provide column address; A10 HIGH enables the
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
NAME (FUNCTION)
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
WRITE Enable
WRITE Inhibit
Table 8, Commands Truth Table, and Table 9, DM
auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
bursts with auto precharge enabled and for WRITE bursts.
BA1 are “Don’t Care.”
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A12 provide the op-
code to be written to the selected mode register.
Commands Truth Table
DM Operation Truth Table
11
CS#
H
description of commands and operations, refer to the
256Mb or 512Mb DDR SDRAM component data sheet.
L
L
L
L
L
L
L
L
256MB, 512MB (x64, DR) PC3200
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS#
X
H
H
H
H
L
L
L
L
CAS#
X
H
H
H
H
L
L
L
L
200-PIN DDR SODIMM
WE#
H
H
H
H
X
L
L
L
L
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
DM
©2004 Micron Technology, Inc.
H
L
NOTES
6, 7
Valid
DQS
1
1
2
3
3
4
5
8
X