MT5VDDT3272AG-40BF1 Micron Technology Inc, MT5VDDT3272AG-40BF1 Datasheet - Page 8

• Manufacturer Part Number: MT5VDDT3272AG-40BF1
• Description: MODULE DDR 256MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT5VDDT3272AG-40BF1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

I
Table 10:
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
per clock cycle; Address and other control inputs changing once per clock
cycle
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
t
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads; BL = 4 with auto precharge;
and control inputs change only during active READ or WRITE commands
DD
CK =
RC =
RC =
CK =
IN
= V
Specifications
t
t
t
t
t
RAS (MAX);
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
CK (MIN); I
CK =
REF
for DQ, DQS, and DM
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
t
t
I
Values are shown for the MT46V8M16 DDR SDRAM only and are computed from values specified in the
128Mb (8 Meg x 16) component data sheet
CK =
CK =
DD
t
CK =
OUT
Specifications and Conditions – 64MB
t
t
t
CK =
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
= 0mA
t
CK (MIN); I
t
CK (MIN); DQ, DM, and DQS inputs changing twice
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
OUT
t
RC =
= 0mA; Address and control inputs
t
RC (MIN);
t
t
CK =
RC =
t
t
REFC =
REFC = 15.625µs
t
t
CK (MIN); Address
RC (MIN);
t
CK =
8
t
RFC (MIN)
t
CK (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
I
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I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1,325
1,925
-335
625
675
225
125
250
725
775
15
25
15
Electrical Specifications
©2002 Micron Technology, Inc. All rights reserved.
1,250
1,875
-262
575
675
225
125
250
700
675
15
25
15
-26A/
1,250
1,875
-265
550
625
200
100
225
675
650
15
25
10
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA