MT4VDDT1664AG-40BF3 Micron Technology Inc, MT4VDDT1664AG-40BF3 Datasheet
MT4VDDT1664AG-40BF3
Specifications of MT4VDDT1664AG-40BF3
Related parts for MT4VDDT1664AG-40BF3
MT4VDDT1664AG-40BF3 Summary of contents
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... SR) PC3200 184-PIN DDR SDRAM UDIMM MT8VDDT1664A – 128MB MT8VDDT3264A – 256MB MT8VDDT6464A – 512MB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 184-Pin DIMM (MO-206) Standard 1.25in. (31.75mm) Low-Profile 1.16in. (29.21mm) OPTIONS • Package 184-pin DIMM (standard) 184-pin DIMM (lead-free) • ...
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Table 2: Part Numbers and Timing Parameters MODULE PART NUMBER DENSITY MT8VDDT1664AG-40B__ 128MB MT8VDDT1664AY-40B__ 128MB MT8VDDT3264AG-40B__ 256MB 256MB MT8VDDT3264AY-40B__ MT8VDDT6464AG-40B__ 512MB MT8VDDT6464AY-40B__ 512MB NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult ...
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Table 3: Pin Assignment (184-Pin DIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL DQ17 47 REF 2 DQ0 25 DQS2 DQ1 DQS0 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS 63, 65, 154 WE#, CAS#, RAS# 16, 17, 75, 76, 137, 138 CK0, CK0#, CK1, CK1#, ...
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... Supply Serial EEPROM positive power supply: +2.3V to +3.6V. DDSPD DNU — Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. NC — No Connect: These pins should be left unconnected. 5 184-PIN DDR SDRAM UDIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... SA0 SA1 SA2 V SS Standard modules use the following DDR SDRAM devices: MT46V16M8TG (128MB); MT46V32M8TG (256MB); MT46V64M8TG (512MB) Lead-free modules use the following DDR SDRAM devices: www.micron.com/ MT46V16M8TP (128MB); MT46V32M8TP (256MB); MT46V64M8TP (512MB) 6 184-PIN DDR SDRAM UDIMM DM4 DM CS# DQS DQ32 ...
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... SA1 SA2 V SS Standard modules use the following DDR SDRAM devices: MT46V16M8TG (128MB); MT46V32M8TG (256MB); MT46V64M8TG (512MB) www.micron.com/ Lead-free modules use the following DDR SDRAM devices: MT46V16M8P (128MB); MT46V32M8P (256MB); MT46V64M8P (512MB) 7 184-PIN DDR SDRAM UDIMM DQS4 DM CS# DQS DQ32 DQ DQ33 ...
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... BA1 select device bank; A0–A11 select device row for the 128MB module, A0–A12 select device row for the 256MB and 512MB modules). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access ...
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... BA0 A10 A8 A11 Operating Mode * M13 and M12 (BA1 and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). 256MB and 512MB Modules BA1 A8 BA0 A12 A11 A10 Operating Mode * M14 and M13 (BA1 and BA0) must be “0, 0” to select the base mode register (vs ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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... DDA8C16_32_64x64AG.fm - Rev. D 9/04 EN 128MB, 256MB, 512MB (x64, SR) PC3200 184-PIN DDR SDRAM UDIMM Figure 7: Extended Mode Register Definition Diagram 128MB Module BA1 BA0 A11 A10 Operating Mode 256MB and 512MB Modules BA1 BA0 A10 A12 A11 Operating Mode E12 E11 E10 E9 ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 128MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 19–21; 0°C ≤ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 13: I Specifications and Conditions – 256MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 19–21; 0°C ≤ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 14: I Specifications and Conditions – 512MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 19–21; 0°C ≤ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions notes appear on pages 19–21; 0°C ≤ T Notes: 1–5, 12–15 CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) notes appear on pages 19–21; 0°C ≤ T Notes: 1–5, 12–15 CHARACTERISTICS PARAMETER Data valid output window REFRESH to REFRESH command interval Average periodic ...
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Notes 1. All voltages referenced Tests for AC timing, Idd, and electrical AC and DC characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are guaranteed for ...
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DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 QHS). ...
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... The current Micron part operates below the slow- est JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 41. For -40B modules specified to be 35mA DD per DDR SDRAM device at 100 MHz. 42. Random addressing changing and 50 percent of data changing at every transfer ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data Validity, and Figure ...
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Table 17: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 18: EEPROM Operating Modes MODE RW BIT Current Address Read 1 0 Random Address ...
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Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 21: Serial Presence-Detect Matrix “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 Number of Row Addresses ...
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Table 21: Serial Presence-Detect Matrix “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” BYTE DESCRIPTION 32 Address And Command Setup Time, 33 Address And Command Hold Time, 34 Data/data Mask Input Setup Time, 35 Data/Data Mask Input Hold Time, 36-40 ...
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Figure 15: 184-Pin DIMM Dimensions – Standard PCB 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) 0.091 (2.30) TYP. TYP. PIN 184 1.95 (49.53) TYP NOTE: All dimensions are in inches ...
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Figure 16: 184-Pin DIMM Dimensions – Low-Profile PCB 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.091 (2.30) 0.050 (1.27) TYP. PIN 184 1.95 (49.53) TYP. NOTE: All dimensions in inches (millimeters); Data ...