MT36VDDF25672G-40BD2 Micron Technology Inc, MT36VDDF25672G-40BD2 Datasheet - Page 9

• Manufacturer Part Number: MT36VDDF25672G-40BD2
• Description: MODULE DDR SDRAM 2GB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36VDDF25672G-40BD2

• Memory Type: DDR SDRAM
• Memory Size: 2GB
• Speed: 200MHz
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 256Mx72
• Total Density: 2GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 3.6A
• Number Of Elements: 36
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1120

General Description
Register and PLL Operation
Serial Presence-Detect Operation
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
The MT36VDDF12872 and MT36VDDF25672 are high-speed, CMOS dynamic random
access 1GB and 2GB memory modules organized in a x72 configuration. These modules
use DDR SDRAM devices with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
These DDR SDRAM modules operate in registered mode, where the control, command,
and address input signals are latched in the registers on the rising clock edge and sent to
the DDR SDRAM devices on the following rising clock edge (data access is delayed by
one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differ-
ential clock signals (CK, CK#) to the DDR SDRAM devices. The register(s) and PLL reduce
control, command, address, and clock signals loading by isolating DRAM from the
system controller. PLL clock timing is defined by JEDEC specifications and ensured by
use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL.
DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module
type and various DDR SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I
which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected
to V
2
C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0],
SS
, permanently disabling hardware write protect.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2002 Micron Technology, Inc. All rights reserved.