MT36VDDF25672G-40BD2 Micron Technology Inc, MT36VDDF25672G-40BD2 Datasheet - Page 15

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MT36VDDF25672G-40BD2

Manufacturer Part Number
MT36VDDF25672G-40BD2
Description
MODULE DDR SDRAM 2GB 184-DIMM
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT36VDDF25672G-40BD2

Memory Type
DDR SDRAM
Memory Size
2GB
Speed
200MHz
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
256Mx72
Total Density
2GByte
Chip Density
512Mb
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
3.6A
Number Of Elements
36
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1120
Register and PLL Specifications
Table 12:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Parameter
DC high-level
input voltage
DC low-level
input voltage
AC high-level
input voltage
AC low-level
input voltage
Output high voltage
Output low voltage
Input current
Static standby
Static operating
Dynamic operating
(clock tree)
Dynamic operating
(per each input)
Input capacitance
(per device, per pin)
Input capacitance
(per device, per pin)
Register Specifications
SSTV16859 devices or equivalent JESD82-4B
Notes:
Symbol
V
V
V
V
I
I
IH
IH
V
IL
IL
V
I
I
DDD
DDD
DD
DD
C
C
OH
I
(
(
OL
(
(
1. Timing and switching specifications for the register listed above are critical for proper oper-
I
DC
AC
DC
AC
I
I
)
)
)
)
ation of the DDR SDRAM RDIMMs. These are meant to be a subset of the parameters for
the specific device used on the module. Detailed information for this register is available in
JEDEC Standard JESD82.
Control, command,
Control, command,
Control, command,
Control, command,
All inputs except
Parity output
Parity output
address
address
address
address
All pins
All pins
All pins
RESET#
RESET#
Pins
n/a
n/a
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
RESET# = V
RESET# = V
or V
CK# switching 50% duty
or V
CK# switching 50% duty
switching at
RESET# = V
V
cycle; One data input
V
I
V
V
15
= V
IL
IL
I
I
RESET# = V
I
(
(
= V
= V
= V
V
AC
AC
Condition
duty cycle
IH
DD
LVCMOS
LVCMOS
SSTL_25
SSTL_25
SSTL_25
SSTL_25
), I
), I
DD
REF
DD
(
I
cycle
Q = 1.8V
AC
O
DD
DD
O
O
Q or V
Q or V
= 0
SS
) or V
±250mV;
, V
, V
= 0; CK and
= 0; CK and
t
CK/2, 50%
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q (I
I
I
SS
= V
= V
Q;
O
IL
SS
SS
(
= 0)
IH
IH
Q
DC
Q
(
(
AC
AC
)
Register and PLL Specifications
)
)
V
V
REF
REF
V
DD
(
(
Min
DC
DC
–5.0
2.5
- 0.2
) + 150
) + 310
©2002 Micron Technology, Inc. All rights reserved.
manufacturer
manufacturer
manufacturer
manufacturer
V
V
REF
REF
Varies by
Varies by
Varies by
Varies by
(
(
Max
+5.0
V
DC
DC
100
0.2
3.5
DD
) - 150
) - 310
Units
mV
mV
mV
mV
mA
µA
µA
µA
µA
pF
pF
V
V

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