MT8LSDT3264HG-13ED2 Micron Technology Inc, MT8LSDT3264HG-13ED2 Datasheet - Page 10

• Manufacturer Part Number: MT8LSDT3264HG-13ED2
• Description: MODULE SDRAM 256MB 144SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8LSDT3264HG-13ED2

• Memory Type: SDRAM
• Memory Size: 256MB
• Speed: 133MHz
• Package / Case: 144-SODIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 144SODIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 548mA
• Number Of Elements: 8
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Commands
able commands. This is followed by written descrip-
tion of each command.
Table 9:
CKE is HIGH for all commands shown except SELF REFRESH
NOTE:
09005aef8077d63a
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
1. A0–A11 (64MB and 128MB) , or A0–A12 (256MB) provide device row address, and BA0, BA1 determine which device
2. A0–A7 (64MB) or A0–A8 (128MB and 256MB) provide device column address; A10 HIGH enables the auto precharge fea-
3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
6. A0–A11 define the op-code written to the mode register; for 64MB and 128MB, A12 should be driven low.
7. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock delay).
The Truth Table provides a quick reference of avail-
bank is made active.
ture (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is
being read from or written to.
BA0, BA1 are “Don’t Care.”
Truth Table – SDRAM Commands and DQMB Operation
For a more detailed des-
CS# RAS# CAS# WE# DQMB
H
L
L
L
L
L
L
L
L
–
–
10
cription of commands and operations, refer to the
64Mb, 128Mb, or 256Mb SDRAM component data
sheet.
64MB, 128MB, 256MB (x64, DR)
H
H
H
H
X
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
–
–
144-PIN SDRAM SODIMM
H
H
H
H
X
L
L
L
L
–
–
L/H
L/H
H
X
X
X
X
X
X
X
L
8
8
Bank/Row
Bank/Col
Bank/Col
©2004 Micron Technology, Inc. All rights reserved.
Op-code
ADDR
Code
X
X
X
X
–
–
High-Z
Active
Active
Valid
DQ
X
X
X
X
X
X
X
NOTES
4, 5
1
2
2
3
6
7
7