MT4LSDT864HG-13EG2 Micron Technology Inc, MT4LSDT864HG-13EG2 Datasheet - Page 19
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MT4LSDT864HG-13EG2
Manufacturer Part Number
MT4LSDT864HG-13EG2
Description
MODULE SDRAM 64MB 144SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT4LSDT864HY-133G2.pdf
(22 pages)
Specifications of MT4LSDT864HG-13EG2
Memory Type
SDRAM
Memory Size
64MB
Speed
133MHz
Package / Case
144-SODIMM
Main Category
DRAM Module
Sub-category
SDRAM
Module Type
144SODIMM
Device Core Size
64b
Organization
8Mx64
Total Density
64MByte
Chip Density
128Mb
Access Time (max)
5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
660mA
Number Of Elements
4
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 65C
Operating Temperature Classification
Commercial
Pin Count
144
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 18: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Table 19: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
NOTE:
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: I
INPUT LEAKAGE CURRENT: V
OUTPUT LEAKAGE CURRENT: V
STANDBY CURRENT:
SCL = SDA = V
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
of SDA.
EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
DD
- 0.3V; All other inputs = GND or 3.3V ±10%
OUT
SS
SS
IN
; V
; V
= 3mA
OUT
= GND to V
DDSPD
DDSPD
= GND to V
= +2.3V to +3.6V
= +2.3V to +3.6V
t
WRC) is the time from a valid stop condition of a write sequence to the end of the
DD
DD
19
SYMBOL
V
V
V
32MB, 64MB, 128MB (x64, SR)
V
I
I
I
I
LO
SB
CC
DD
OL
LI
IH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IL
SYMBOL
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
t
t
HIGH
LOW
f
WRC
t
t
BUF
SCL
AA
DH
t
t
t
F
R
I
144-PIN SDRAM SODIMM
V
DD
MIN
-1
3
–
–
–
–
–
x 0.7
MIN
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
V
V
DD
DD
MAX
MAX
©2004 Micron Technology, Inc. All rights reserved.
300
400
0.9
0.3
3.6
0.4
50
10
10
10
30
2
+ 0.5
x 0.3
UNITS
KHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
UNITS
mA
µA
µA
µA
V
V
V
V
NOTES
1
2
2
3
4