MT4VDDT3264AY-40BF1 Micron Technology Inc, MT4VDDT3264AY-40BF1 Datasheet - Page 12

• Manufacturer Part Number: MT4VDDT3264AY-40BF1
• Description: MODULE DDR 256MB 184-UDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3264AY-40BF1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 200MHz
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 860mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1342

Serial Presence-Detect
Table 12:
Table 13:
Serial Presence-Detect Data
PDF: 09005aef8085081a/Source: 09005aef806e129d
DD4C16_32x64A.fm - Rev. E 11/08 EN
Parameter/Condition
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: Iout = 3mA
Input leakage current: Vin = GND to Vdd
Output leakage current: Vout = GND to Vdd
Standby current: SCL = SDA = Vdd - 0.3V; All other inputs = Vss or Vdd
Power supply current: SCL clock frequency = 100 kHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA fall time
SDA rise time
Data-in hold time
Start condition hold time
Clock HIGH period
Clock LOW period
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
Serial Presence-Detect EEPROM AC Operating Conditions
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
128MB, 256MB (x64, SR) 184-Pin DDR SDRAM UDIMM
12
t
t
Symbol
t
t
t
WRC) is the time from a valid stop condition of a write
t
HD:DAT
t
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
t
HD:DI
t
HIGH
LOW
f
WRC
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BUF
SCL
AA
t
t
R
F
Symbol
VddSPD
Vih
Vol
Isb
Vil
Ilo
Icc
Ili
Min
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
–
–
0
–
–
VddSPD × 0.7 VddSPD + 0.5
Min
–1.0
2.3
Serial Presence-Detect
–
–
–
–
–
Max
300
300
400
0.9
–
–
–
–
–
–
–
–
–
5
©2003 Micron Technology, Inc. All rights reserved.
VddSPD × 0.3
Units
kHz
ms
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
µs
µs
Max
3.6
0.4
2.0
10
10
30
Notes
Units
1
2
2
3
4
mA
µA
µA
µA
V
V
V
V