TH58NS512DC-TO51(Y) Toshiba, TH58NS512DC-TO51(Y) Datasheet
TH58NS512DC-TO51(Y)
Specifications of TH58NS512DC-TO51(Y)
TH58NS512DCTO51Y
Related parts for TH58NS512DC-TO51(Y)
TH58NS512DC-TO51(Y) Summary of contents
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... The TH58NS512DC is a SmartMedia device. This unique ID number is applicable to image files, music files, electronic books, and so on where copyright protection is required. The data stored in the TH58NS512DC needs to comply with the data format standardized by the SSFDC Forum in order to maintain compatibility with other SmartMedia FEATURES Organization • ...
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... The information contained herein is subject to change without notice. Status register Address register Command register Control circuit HV generator PARAMETER PARAMETER CONDITION OUT TH58NS512DC Column buffer Column decoder Data register Sense amp Memory cell array Extended area (embedded ID) RATING −0.6~4.6 −0.6~4.6 − ...
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... I IL OUT = cycle = cycle = cycle = cycle − 0 −400 µ 2 0 Pin V OL TH58NS512DC MIN TYP. MAX 4016 4096 MIN TYP. MAX 3 3.3 3.6 −0.3* 0.8 MIN TYP. MAX ±10 ±10 ...
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... CE High to Ready (When interrupted Read Mode) CRY t Device Reset Time (Read/Program/Erase) RST AC TEST CONDITIONS PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load PARAMETER TH58NS512DC MIN MAX UNIT ...
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... Refer to Application Note (15) toward the end of this document. is greater than or equal to 100 ns. CEH signal stays Ready. t CEH 526 527 A Busy MIN TH58NS512DC pin. ≥ 100 0~30 ns → Busy signal is not output. A TYP. MAX UNIT µs 200 1000 ...
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... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O1 ~I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE I/O1 ~I/O8 Setup time CLH ALH TH58NS512DC Hold time 2000-08-27 6/33 ...
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... Address Input Cycle Timing Diagram t CLS CLE ALS ALE I/O1 ~I/O8 Data Input Cycle Timing Diagram CLE CE t ALS ALE WE I/O1 ~I/ A0~A7 A9~A16 TH58NS512DC ALH A17~A24 A25 : CLH 527 2000-08-27 7/33 ...
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... Serial Read Cycle Timing Diagram REA I/O1 ~I/ Status Read Cycle Timing Diagram CLE t CLS I/O1 ~I/ 70H represents the hexadecimal number 70 REH RHZ REA RHZ t CLS t CLH WHC CSTO t WHR 70H* TH58NS512DC CHZ CHZ RSTO RHZ Status output : 2000-08-27 8/33 ...
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... Column address Read Operation using 00H Command N: 0~255 t t ALH AR2 A17 A25 ~A16 ~A24 t t ALH AR2 A17 A25 ~A16 ~A24 TH58NS512DC REA OUT OUT OUT OUT 527 : CHZ RHZ t t REA OUT OUT OUT 2000-08-27 9/33 t CEH t CRY t RB ...
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... DS DH I/O1 50H ~I/ Read Operation using 50H Command N: 0~15 t ALH A17 A0~A7 A9~A16 A25 ~A24 Column address N* t ALH A17 A0~A7 A9~A16 A25 ~A24 Column address N* TH58NS512DC t AR2 REA D D OUT OUT 256 + M 256 + AR2 REA D D OUT OUT 512 + M 512 + ...
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... Sequential Read (2) Timing Diagram CLE CE WE ALE RE I/O1 A0 01H ~A7 ~A16 ~I/O8 Column address A17 A25 N ~A24 Page t R address M Page M access A9 A17 A25 ~A24 Page t 256 + 256 + R address Page M access TH58NS512DC 527 Page access : 527 256 + Page access : 2000-08-27 11/33 527 527 ...
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... Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 A0 50H ~A7 ~A16 ~I/O8 Column address A17 A25 ~A24 Page t 512 + 512 + R address Page M access TH58NS512DC 527 512 513 514 t 512 + Page access : 2000-08-27 12/33 527 ...
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... IN ~A24 : not input data while data is being output ALH WB BERASE A25 D0H Erase Start Busy command : not input data while data is being output TH58NS512DC t PROG 10H 70H 527 Erase Start Status Read command command Status 70H output Status Read command 2000-08-27 13/33 ...
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... ID Read Operation Timing Diagram CLE t CLS ALH ALE I/O1 90H ~I/O8 t CLS ALS ALH AR1 t 00 Address input TH58NS512DC t t REAID REAID REAID 98H 76H Maker code Device code Option code : 2000-08-27 14/33 A5H ...
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... after completion of the operation. The output buffer for this signal is an open drain. Low Voltage Detect: LVD The LVD signal is used to detect the power supply voltage level L), such as during a Program or Erase operation, and will not enter REA TH58NS512DC TH58NS512DC CLE ALE ...
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... Table 1. 8I/O I/O6 I/O5 I/O4 I/O3 I/ A14 A13 A12 A11 A10 A22 A21 A20 A19 A18 * CLE ALE TH58NS512DC I/O1 A0~A7: Column address A0 A9~A25: Page address A9 A14~A25: Block address A9~A13: NAND address in block A17 A25 2000-08-27 16/ ...
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... Output Deselect L Standby Second Cycle Acceptable while Busy D0 ALE TH58NS512DC HEX data bit assignment (Example) Serial data input: 80H I/ I/O1 I/O1~I/O8 Power L Data output Active H High impedance Active * High impedance Standby 2000-08-27 17/33 ...
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... The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer set after column address 256, use Read mode (2). However, for a Sequential Read, output of the next page Cell array starts from column address 0. TH58NS512DC 2000-08-27 18/33 ...
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... A4-to-A7 address. (An 00H command is necessary to move the pointer back to the 0-to-511 main memory cell location.) Data output t R Busy 527 (01H) A Sequential Read (2) TH58NS512DC Data output Busy Busy (50H) 512 527 A Sequential Read (3) ...
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... Device Device 2 3 Busy 70H Status on Device 1 Figure 6. Status Read timing application example pin signals from multiple devices are wired together as shown in the TH58NS512DC The Pass/Fail status on I/O1 is only valid when the device is in the Ready state Device Device Status on Device N ...
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... After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. D0 Busy TH58NS512DC Pass 70 I/O Status Read Fail command ...
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... Internal When a Reset (FFH) command is input during erasing D0 Internal erase voltage When a Reset (FFH) command is input during a Read operation TH58NS512DC FF Register set (max 10 µs) t RST FF Register set (max 500 µs) t RST FF (max 6 µs) t RST 2000-08-27 22/33 Figure 8. 00 Figure 9. 00 Figure 10 ...
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... When two or more Reset commands are input in succession The second 70 ( command is invalid, but the third TH58NS512DC Figure 11. I/O status: Pass/Fail → Pass Ready/Busy → Ready I/O status: Ready/Busy → Busy Figure 12. (2) ( command is valid. 2000-08-27 23/33 ...
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... CR t AR1 t REAID 00 98H Maker code and t refer to the AC Characteristics. REAID CR AR1 Figure13. ID Read timing I/O7 I/O6 I/O5 I/ TH58NS512DC 76H Device code I/O3 I/O2 I/O1 Hex Data 98H 76H A5H* 2000-08-27 24/33 A5H Option code ...
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... Address Start point B area A area Address DIN ↓ Start point C area Address DIN ↓ Start point B area Figure 15. Example of How to Set the Pointer TH58NS512DC 255 256 511 A B 00H 01H Pointer control 50H Figure 14. Pointer control 50H Address Start point C area ...
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... If the programming result for page address M is Fail, do not try to program the 10 page to address N in another block. Because the previous input data has been lost, the same input sequence of 80H command, address and data is necessary. TH58NS512DC For this operation the FFH command is needed. 00 [A] ...
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... CLE, ALE Ready 1.5 µs 1.0 µ 0.5 µ KΩ FF Reset Figure 20 Operation Figure 21. Power-on/off Sequence TH58NS512DC buffer consists of an open drain 3.0 V Busy 1 3 25° 100 KΩ 3 KΩ 4 KΩ R Don’t care V IL 2000-08-27 27/ ...
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... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE DIN (100 ns min) WW Enable Erasing WE DIN (100 ns min) WW Disable Erasing WE DIN (100 ns min TH58NS512DC 2000-08-27 28/33 ...
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... Although the device may read in a fourth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H, 50H Internal read operation starts when WE goes High in the third cycle. Program operation CLE CE WE ALE I/O 80H Address input Figure 22. Address input Ignored Figure 23. TH58NS512DC Ignored Data input 2000-08-27 29/33 ...
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... Busy state. (Refer to Figure 25.) I/O 00H/01H/50H Hence the RE clock input must start after the address input. Data Pattern 2 All 1s Data Pattern 2 Figure 24. be set to all 1). Figure 25. TH58NS512DC All 1s All 1s Data Pattern 10 Data Pattern 10 Address input 2000-08-27 30/33 ...
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... This chattering may cause damage to the data in the TH58NS512DC. Therefore, sufficient time must be allowed for contact bouncing to subside when a system is designed with SmartMedia (17) The TH58NS512DC is formatted to comply with the Physical and Logical Data Format of the SSFDC Forum at the time of shipping. Referring to the Block status area in the redundant area allows the system to detect bad blocks in the accordance with the physical data format issued by the SSFDC Forum ...
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... Some electrical specifications in this data sheet show differences from the Forum’s electrical specification. Complying with the Forum’s electrical specification maintains compatibility with other SmartMedias. Please refer folloing SSFDC Forum’s URL to get the detailed information of each specification. URL http://www.ssfdc.or. especially with large capacity SmartMedia TH58NS512DC small removable TM . 2000-08-27 32/33 ...
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... PACKAGE DIMENSIONS • FDC-22C TH58NS512DC Unit: mm 2000-08-27 33/33 ...