HCPL-4562 Avago Technologies US Inc., HCPL-4562 Datasheet - Page 16

• Manufacturer Part Number: HCPL-4562
• Description: OPTOCOUPLER HI BAND 17MHZ 8DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-4562

• Input Type: DC
• Package / Case: 8-DIP (0.300", 7.62mm)
• Number Of Channels: 1
• Voltage - Isolation: 3750Vrms
• Voltage - Output: 20V
• Current - Output / Channel: 8mA
• Current - Dc Forward (if): 12mA
• Output Type: Transistor with Vcc
• Mounting Type: Through Hole
• Isolation Voltage: 3750 Vrms
• Minimum Forward Diode Voltage: 1.1 V
• Output Device: Phototransistor
• Configuration: 1 Channel
• Current Transfer Ratio: 45 %
• Maximum Forward Diode Voltage: 1.6 V
• Maximum Reverse Diode Voltage: 1.8 V
• Maximum Input Diode Current: 12 mA
• Maximum Power Dissipation: 100 mW
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Vce Saturation (max): -
• Current Transfer Ratio (max): -
• Current Transfer Ratio (min): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 516-1052-5

Conversion from HCPL-4562 to HCNW4562
In order to obtain similar circuit performance when
converting from the HCPL-4562 to the HCNW4562,
it is recommended to increase the Quiescent Input
Current, I
in Figure 4 is used, then potentiometer R4 should be
adjusted appropriately.
Design Considerations of the Application Circuit
The appÏication circuit in Figure 4 incorporates
several features that help maximize the bandwidth
performance of the HCPL-4562/HCNW4562. Most
important of these features is peaked response of the
detector circuit that helps extend the frequency range
over which the voltage gain is relatively constant. The
number of gain stages, the overall circuit topology, and
the choice of DC bias points are all consequences of
the desire to maximize bandwidth performance.
To use the circuit, first select R
LED quiescent current by:
For a constant value V
(adjusting the gain with R
keeping the modulation factor (MF) dependent only
on V
F actor ( MF ) :
V
Modulation
F actor ( MF ) :
F actor ( MF ) :
V
F actor ( MF ) :
For a given G
F actor ( MF ) :
only with h
F actor ( MF ) :
V
V
V
V
Where:
and,
16
where typically
I
i
I
I
i
I
I
i
I
i
i
O
i
I
O
O
I
I
O
O
O
I
I
I
I
I
I
I
I
I
i
i
i
i
i
i
F p-p
F p-p
F p-p
F p-p
F p-p
F p-p
I
R
I
I
R
G
I
I
I
R
G
R
R
F Q
F Q
F Q
F Q
F Q
F Q
PB Q
B XQ
PB Q
PB Q
B XQ
PB Q
PB Q
PB Q
B XQ
B XQ
B XQ
B XQ
I
I
I
I
I
I
F p-p
F p-p
F p-p
F p-p
F p-p
F p-p
R
R
R
R
R
R
CQ4
CQ4
CQ4
CQ4
CQ4
CQ4
p-p
p-p
p-p
p-p
p-p
p-p
F Q
F Q
= V
F Q
F Q
F Q
= V
F Q
= V
= V
= V
= V
10
10
10
10
V
V
p-p
p-p
p-p
p-p
p-p
p-p
Q4
Q4
Q4
Q4
Q4
Q4
9
9
9
9
9
9
E
=
=
=
=
=
=
.
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
*
*
*
*
*
≈
≈
≈
≈
≈
≈
CC
CC
CC
CC
CC
CC
V
R
V
R
V
R
V
V
R
V
R
R
V
V
1 + s R
1 + s R
1 + s R
1 + s R C
V
≈
V
≈
V
≈
V
V
V
≈
≈
≈
V
V
V
V
V
V
V
E
E
E
E
E
E
G
G
G
G
G
G
OUT
OUT
4
4
4
4
4
4
FQ
IN
IN
IN
IN
IN
IN
R
R
R
R
R
R
IN
CC
CC
CC
CC
CC
CC
– V
– V
– V
– V
– V
– V
V
V
V
V
V
V
i
i
i
i
i
i
V
V
R
V
V
R
V
V
R
R
R
R
I
I
I
I
I
I
, from 6 mA to 10 mA. If the application circuit
PB p-p
PB p-p
PB p-p
PB p-p
PB p-p
PB p-p
R
R
R
R
R
R
11
11
11
11
11
11
/R
/R
/R
/R
/R
/R
FEX
O
O
O
O
O
O
≈
≈
PB Q
≈
≈
≈
≈
PB Q
PB Q
PB Q
PB Q
PB Q
6
6
6
6
6
6
V
V
V
V
V
V
7
7
7
7
7
7
- 2 V
- 2 V
- 2 V
- 2 V
- 2 V
- 2 V
p-p
p-p
p-p
B E
p-p
p-p
p-p
B E
B E
B E
B E
B E
.
≈
≈
4
4
4
4
4
4
R
R
R
R
R
R
E
E
E
E
E
E
h
h
h
h
h
h
( I
( I
( I
( I
( I
( I
V
R
, V
R
R
R
R
R
i
2 I
i
2 I
i
2 I
i
i
i
2 I
2 I
2 I
9
F E X
9
9
F E X
9
9
9
F E X
F E X
F E X
F E X
4
4
4
4
4
4
F ( p-p)
F ( p-p)
F ( p-p)
F ( p-p)
F ( p-p)
F ( p-p)
–
–
–
–
–
–
9
9
9
10
10
10
10
10
10
=
=
=
=
=
=
G
G
G
G
G
G
4.25 V
4.25 V
4.25 V
I
4.25 V
4.25 V
4.25 V
I
PB
PB
PB
PB
PB
PB
470
470
470
470
470
470
( p-p)
( p-p)
( p-p)
( p-p)
( p-p)
E
( p-p)
I
PB
PB
F Q
F Q
F Q
, and V
F Q
F Q
F Q
F
B E
B E
B E
B E
B E
B E
V
V
V
V
V
V
C
C
C
R
R
R
R
R
R
/ I
/ I
/ I
/ I
/ I
/ I
V
V
V
V
V
V
I
R
R
R
R
R
R
I
CQ
CQ
CQ
PB
V
V
V
V
V
V
INp-p
INp-p
INp-p
INp-p
INp-p
INp-p
F
10
10
10
10
10
10
V
V
V
V
V
V
9
9
9
9
9
9
E
E
E
E
E
E
R
F
F
F
F
F
F
E
E
E
E
E
E
=
=
=
=
=
=
R
R
p-p
p-p
p-p
p-p
p-p
p-p
3
3
3
[ V
[ V
[ V
[ V
[ V
[ V
) R
) R
) R
) R
) R
) R
1
1
1
1
1
1
R
R
R
R
R
R
4
V
V
V
V
V
V
7
7
+
+
+
+
R
R
= 0.0032
R
10
10
10
10
10
2 V
10
2 V
2 V
2 V
2 V
2 V
B E X
B E X
CC
B E X
B E X
B E X
B E X
INp-p
INp-p
INp-p
INp-p
INp-p
INp-p
10
7
7
7
7
7
7
9
9
9.0 mA
9.0 mA
9.0 mA
9.0 mA
9.0 mA
9.0 mA
, DC output voltage will vary
2 R
2 R
2 R
R
R
R
R
R
R
INp-p
p-p
p-p
p-p
p-p
p-p
p-p
E
E
E
E
E
E
9
9
9
9
9
9
- ( I
- ( I
- ( I
- ( I
- ( I
- ( I
4
) preserves linearity by
1
, the circuit topology
1
1
1
1
1
11
11
11
to set V
PB Q
PB Q
PB Q
PB Q
PB Q
PB Q
f
f
f
T 4
T 4
T 4
4
4
4
- I
- I
- I
- I
- I
- I
B XQ
B XQ
B XQ
B XQ
B XQ
B XQ
E
for the desired
) R
) R
) R
) R
) R
) R
7
7
7
7
7
7
]
]
]
]
]
]
( 10)
( 10)
( 5)
( 5)
( 5)
( 5)
( 5)
( 5)
( 8)
( 9)
( 8)
( 8)
( 9)
( 8)
( 8)
( 8)
( 9)
( 9)
( 9)
( 1)
( 1)
( 3)
( 1)
( 4)
( 1)
( 1)
( 3)
( 1)
( 3)
( 4)
( 3)
( 3)
( 4)
( 3)
( 6)
( 4)
( 4)
( 4)
( 7)
( 6)
( 6)
( 7)
( 6)
( 6)
( 6)
( 7)
( 7)
( 7)
( 7)
( 2)
( 2)
( 2)
( 2)
( 2)
( 2)
Figure 15 shows the dependency of the DC output
voltage on h
F actor ( MF ) :
For 9 V < V
V
The voltage gain of the second stage (Q
approximately equal to:
Increasing R′
R
R
If it is necessary to drive a low impedance load,
bandwidth may also be preserved by adding an
additional emitter following the buffer stage (Q
Figure 16), in which case R
set I
Finally, adjust R
Definition:
where typically
where typically
where typically
I
I
I
I
O
I
I
11
9
V
C
i
I
I
R
R
G
G
I
R
G
F p-p
PB Q
PB Q
B XQ
B XQ
PB Q
B XQ
/R
i
I
R
R
R
V
F p-p
h
CQ4
CQ4
CQ4
PB
i
IN
I
I
CQ
p-p
F Q
= V
f
10
10
10
F
PBQ
BXQ
p-p
V
V
V
G
Q4
Q4
and the load impedance) or reducing R
Q4
I
BEX
FEX
9
9
9
CQ4
V
T
10
p-p
p-p
p-p
FQ
4
3
≈
≈
≈
V
E
≈
≈
≈
≈
≈
*
≈
*
ratio constant) will improve the bandwidth.
*
= Voltage Gain
= Quiescent LED forward current
= Peak-to-peak small signal LED forward
= Peak-to-peak small signal input voltage
= Peak-to-peak small signal
= Quiescent base photo current
= Base-Emitter voltage of HCPL-4562/
= Quiescent base current of HCPL-4562/
= Current Gain (I
= Voltage across emitter degeneration
= Unity gain frequency of Q
= Effective capacitance from collector of Q
≈
≈
≈
CC
≅ 2 mA.
V
V
V
1 + s R
1 + s R
1 + s R
≈
V
V
V
V
V
V
OUT
OUT
OUT
G
G
G
current
base photo current
HCNW4562 transistor
HCNW4562 transistor
HCNW4562 transistor
resistor R
to ground
IN
R
R
R
IN
IN
IN
CC
CC
CC
V
– V
V
V
i
V
V
R
R
V
R
I
CC
PB p-p
R
R
11
11
R
11
O
O
O
PB Q
6
6
6
V
V
V
7
7
FEX
7
- 2 V
< 12 V, select the value of R
- 2 V
- 2 V
11
B E
p-p
≈
≈
≈
4
R
R
R
E
E
E
h
h
h
R
R
.
R
(R′
9
9
i
2 I
F E X
F E X
9
F E X
4
4
F ( p-p)
–
9
9
9
10
10
10
=
4.25 V
4.25 V
I
I
4.25 V
I
470
470
470
to achieve the desired voltage gain.
I
I
I
( p-p)
PB
PB
PB
11
F Q
F
F
F
B E
B E
B E
C
C
C
4
R
V
I
I
I
R
includes the parallel combination of
I
I
I
CQ
CQ
CQ
PB
PB
PB
10
INp-p
10
F
F
F
V
9
R
R
R
E
=
R
R
R
p-p
3
3
3
[ V
1
1
1
4
4
4
V
7
7
7
C
+
+
+
R
R
R
/I
2 V
R
R
= 0.0032
= 0.0032
R
= 0.0032
INp-p
B E X
10
10
10
B
9
9
9
9.0 mA
9.0 mA
9.0 mA
) of HCPL-4562/
2 R
2 R
2 R
p-p
E
- ( I
11
1
1
1
11
11
11
PB Q
can be increased to
f
f
f
5
T 4
T 4
T 4
4
4
4
- I
B XQ
11
such that
) R
9
7
]
(keeping
3
( 10)
( 10)
( 10)
3
( 5)
) is
5
( 8)
( 8)
( 9)
( 9)
( 8)
( 9)
( 6)
( 3)
( 6)
( 7)
( 4)
( 7)
( 6)
( 7)
in